config.cpp

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

	// Clear the "valid" bits in the memory controller
	// This must be done before enabling compression so that the display
	// controller doesn't accidently read what it thinks to be a compressed
	// line.  The size of the RAM in the memory controller is 1024 bits,
	// which is cleared though registers specifying the index and data value.

	for (value = 0; value < 1024; value++) {
		WRITE_REG32(GXregisters, MC_DR_ADD, value);
		WRITE_REG32(GXregisters, MC_DR_ACC, 0x0);
	}
#endif

#ifdef DURANGO
	modeId = gfx_set_display_mode(pMode->gpeMode.width,
		pMode->gpeMode.height, pMode->gpeMode.Bpp, 75);
	RETAILMSG( 1, ( TEXT("Durango mode set to = %d %d %d\n"), 
		pMode->gpeMode.width,pMode->gpeMode.height, pMode->gpeMode.Bpp ) );

	//Set the BPP 
//	WRITE_REG32(GXregisters, DC_CURS_ST_OFFSET, pMode->curs_offset);
	gfx_set_cursor_position(pMode->curs_offset,0,0,0,0); 
	gfx_set_cursor_enable(1);


#else 	//hrhr

	// UNLOCK THE DISPLAY CONTROLLER REGISTERS
	Unlock();

	// READ THE CURRENT GX VALUES
    gcfg = READ_REG32(GXregisters, DC_GENERAL_CFG);
	DEBUGMSG( 0,(TEXT("DC_GENERAL_CFG %08X\n"),gcfg));
    tcfg = READ_REG32(GXregisters, DC_TIMING_CFG);
    ocfg = READ_REG32(GXregisters, DC_OUTPUT_CFG);

	// READ THE CURRENT CX5530 VALUES AND BLANK THE CX5530 DISPLAY
 	dcfg30 = READ_REG32(CX5530registers, CX55xx_DISPLAY_CONFIG);
	dcfg30 &= ~(unsigned long) (CX5530_DCFG_DAC_BL_EN
		      | CX5530_DCFG_DIS_EN    | CX5530_DCFG_HSYNC_EN | CX5530_DCFG_VSYNC_EN
		      | CX5530_DCFG_FP_PWR_EN | CX5530_DCFG_FP_DATA_EN );

   	WRITE_REG32(CX5530registers, CX55xx_DISPLAY_CONFIG, dcfg30);

    // BLANK THE DISPLAY
    tcfg &= ~(unsigned long)DC_TCFG_BLKE;
    WRITE_REG32(GXregisters, DC_TIMING_CFG, tcfg);

    // DISABLE THE TIMING GENERATOR
    tcfg &= ~(unsigned long)DC_TCFG_TGEN;						  
    WRITE_REG32(GXregisters, DC_TIMING_CFG, tcfg);

	// DELAY: WAIT FOR PENDING MEMORY REQUESTS 
	// This delay is used to make sure that all pending requests to the 
	// memory controller have completed before disabling the FIFO load.
	delay_milliseconds();

    // DISABLE DISPLAY FIFO LOAD AND DISABLE COMPRESSION
    gcfg &= ~(unsigned long)(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
	DEBUGMSG( 0,(TEXT("DC_GENERAL_CFG %08X\n"),gcfg));
    WRITE_REG32(GXregisters, DC_GENERAL_CFG, gcfg);

	// CLEAR THE "DCLK_MUL" FIELD 
	gcfg &= ~(unsigned long)(DC_GCFG_DDCK | DC_GCFG_DPCK | DC_GCFG_DFCK);
	DEBUGMSG( 0,(TEXT("DC_GENERAL_CFG %08X\n"),gcfg));
	gcfg &= ~(unsigned long)DC_GCFG_DCLK_MASK;
	DEBUGMSG( 0,(TEXT("DC_GENERAL_CFG %08X\n"),gcfg));
	WRITE_REG32(GXregisters, DC_GENERAL_CFG, gcfg);

#ifdef DD_SUPPORT
    if (DeviceId == DHRUVA) { 
	    WRITE_REG32(CX5530registers, DHRUVA_MISC, DHRUVA_MISC_DATA);
	    WRITE_REG32(CX5530registers, DHRUVA_PLL_CLOCK, DHRUVA_PLL_CLOCK_DATA);
    } else 
#endif //DD_SUPPORT
	{
		if(DeviceId == CX5510)
			cx55xx_clock = 	pMode->cx55xx_clock;
		else if(DeviceId == CX5520)
			cx55xx_clock = 	pMode->cx5520_clock;
		else if(DeviceId == CX5530)
			cx55xx_clock = 	pMode->cx5530_clock;

		// SET THE DOT CLOCK FREQUENCY & SET THE RESET BIT
		WRITE_REG32(CX5530registers, CX55xx_DOT_CLK_CONFIG, cx55xx_clock | 0x80000000);

		// K1.2 Nick Mati - clear PLL out from max Vco
		WRITE_REG32(CX5530registers, CX55xx_DOT_CLK_CONFIG, cx55xx_clock | 0x80000100);	
		delay_milliseconds();
		WRITE_REG32(CX5530registers, CX55xx_DOT_CLK_CONFIG, cx55xx_clock | 0x80000000);		
		// K1.2

		// PROGRAM THE CLOCK FREQUENCY
		WRITE_REG32(CX5530registers, CX55xx_DOT_CLK_CONFIG, cx55xx_clock);
	}
	// DELAY: WAIT FOR THE PLL TO SETTLE
	// This allows the dot clock frequency that was just set to settle.
	delay_milliseconds();

	// SET THE "DCLK_MUL" FIELD OF DC_GENERAL_CFG
	// The GX hardware divides the dot clock, so 2x really means that the 
	// internal dot clock equals the external dot clock. 

	gcfg |= pMode->gcfg & DC_GCFG_DCLK_MASK;
	DEBUGMSG( 0,(TEXT("DC_GENERAL_CFG %08X\n"),gcfg));
	WRITE_REG32(GXregisters, DC_GENERAL_CFG, gcfg);
	
	// DELAY: WAIT FOR THE ADL TO LOCK
	// This allows the clock generatation within GX to settle.  This is 
	// needed since some of the register writes that follow require that 
	// clock to be present. 

	delay_milliseconds();

	// SET THE DISPLAY CONTROLLER PARAMETERS
	WRITE_REG32(GXregisters, DC_FB_ST_OFFSET, pMode->fb_offset);
	WRITE_REG32(GXregisters, DC_CB_ST_OFFSET, pMode->cb_offset);
	WRITE_REG32(GXregisters, DC_CURS_ST_OFFSET, pMode->curs_offset);
	WRITE_REG32(GXregisters, DC_LINE_DELTA, pMode->line_delta);
	WRITE_REG32(GXregisters, DC_BUF_SIZE, pMode->buffer_size);
	WRITE_REG32(GXregisters, DC_H_TIMING_1, pMode->htiming1);
	WRITE_REG32(GXregisters, DC_H_TIMING_2, pMode->htiming2);
	WRITE_REG32(GXregisters, DC_H_TIMING_3, pMode->htiming3);
	WRITE_REG32(GXregisters, DC_FP_H_TIMING, pMode->fp_htiming);
	WRITE_REG32(GXregisters, DC_V_TIMING_1, pMode->vtiming1);
	WRITE_REG32(GXregisters, DC_V_TIMING_2, pMode->vtiming2);
	WRITE_REG32(GXregisters, DC_V_TIMING_3, pMode->vtiming3);
	WRITE_REG32(GXregisters, DC_FP_V_TIMING, pMode->fp_vtiming);

	// COPY NEW GX CONFIGURATION VALUES
	gcfg = pMode->gcfg;
	tcfg = pMode->tcfg;
	ocfg = pMode->ocfg;

	// MODIFY GX CONFIGURATION FOR CX5530, IF NEEDED

	// SET SYNC POLARITIES
	// For CX5530 systems, the GX is always programmed so that it 
	// gemerates positive sync polarities (pulse from low to high).  
	// The CX5530 then reverses the polarities, if needed.

	dcfg30 &= ~(unsigned long) CX5530_DCFG_CRT_HSYNC_POL;
	dcfg30 &= ~(unsigned long) CX5530_DCFG_CRT_VSYNC_POL;
	dcfg30 &= ~(unsigned long) CX5530_DCFG_FP_HSYNC_POL;
	dcfg30 &= ~(unsigned long) CX5530_DCFG_FP_VSYNC_POL;
	if (pMode->hsync_pol == 0) dcfg30 |= CX5530_DCFG_CRT_HSYNC_POL;
	if (pMode->vsync_pol == 0) dcfg30 |= CX5530_DCFG_CRT_VSYNC_POL;
	if (tcfg & DC_TCFG_FHSP) dcfg30 |= CX5530_DCFG_FP_HSYNC_POL;
	if (tcfg & DC_TCFG_FVSP) dcfg30 |= CX5530_DCFG_FP_VSYNC_POL;
	tcfg &= ~(unsigned long) (DC_TCFG_CHSP | DC_TCFG_CVSP);
	tcfg &= ~(unsigned long) (DC_TCFG_FHSP | DC_TCFG_FVSP);

	// PROGRAM THE CONFIGURATION REGISTERS (MUST BE IN THIS SEQUENCE)

	WRITE_REG32(GXregisters, DC_OUTPUT_CFG, pMode->ocfg);
	WRITE_REG32(GXregisters, DC_TIMING_CFG, pMode->tcfg);

	value = pMode->gcfg; //store in temp variable
	DEBUGMSG( 0,(TEXT("DC_GENERAL_CFG new value %08X\n"),value));

#if COMPRESSION_ENABLE
	// Enable compression
	// Compression (writes) and decompression (reads) have separate enable
	// bits for hardware debug purposes.  Always enable both.
	value |= (DC_GCFG_CMPE | DC_GCFG_DECE);
#endif

#ifdef DD_SUPPORT
	value |= DC_GCFG_VRDY;
#endif //DD_SUPPORT

	DEBUGMSG( 0,(TEXT("DC_GENERAL_CFG new value %08X\n"),value));
	WRITE_REG32(GXregisters, DC_GENERAL_CFG, value);

	// ENABLE 5530 DISPLAY

	// ENABLE DISPLAY

	dcfg30 |= CX5530_DCFG_DIS_EN;
	dcfg30 |= CX5530_DCFG_HSYNC_EN;
	dcfg30 |= CX5530_DCFG_VSYNC_EN;
		
	// ENABLE CRT OUTPUT

	dcfg30 |= CX5530_DCFG_DAC_BL_EN;
	dcfg30 |= CX5530_DCFG_DAC_PWDNX;

	// ENABLE FLAT PANEL OUTPUT

	dcfg30 |= CX5530_DCFG_FP_PWR_EN;
	dcfg30 |= CX5530_DCFG_FP_DATA_EN;

	// PICK WHICH DATA STREAM GOES THROUGH THE PALETTE
	// For this file, this is always the video stream.

	dcfg30 |= CX5530_DCFG_GV_PAL_BYP;
	WRITE_REG32(CX5530registers, CX55xx_DISPLAY_CONFIG, dcfg30);

	// Setting the BPP and stride in Graphics pipeline

	value = (m_nScreenStride > 1024) ? 0x200 : 0; 
	value |= (m_pMode->Bpp > 8) ? 0x100 : 0;
	WRITE_REG32(GXregisters, GP_BLIT_STATUS, value);


	// RESTORE LOCK OF DC_UNLOCK
	Lock();
	WRITE_REG32(GXregisters, DC_CURS_ST_OFFSET, pMode->curs_offset);
	Unlock();

    gcfg = READ_REG32(GXregisters, DC_GENERAL_CFG);
    gcfg |= DC_GCFG_CURE;						 
	WRITE_REG32(GXregisters, DC_GENERAL_CFG, gcfg); 
    
	Lock();	

#endif //hrhr

	Display_BPP = m_pMode->Bpp;                       

	if (Display_BPP == 8)							  	
		BB0_Size_Pixels = BB0_Size_Bytes;			  
	else											  
		BB0_Size_Pixels = BB0_Size_Bytes >> 1;		  	

	// clear the screen
#ifdef DD_SUPPORT
//	int fbWidth = 1024;
	//unsigned short *pBuf = (unsigned short *)m_pPrimarySurface->Buffer();
//#ifdef FB16BPP
	unsigned short *pBuf = (unsigned short *) (pDriverData->FbLinear);
//#else
//#endif
    for( int fbrow=0;fbrow<m_nScreenHeight; fbrow++ ) {
		for(int fbcol=0;fbcol<m_nScreenStride;fbcol++) {
		    *pBuf++=0;
		}
    }
#else
	int fbWidth = ((m_nScreenStride > 1024) ? 2048 : 1024);
	unsigned char *pBuf = (unsigned char *)m_pPrimarySurface->Buffer();
		memset(pBuf, 0x0, (m_nScreenHeight * fbWidth));
#endif //DD_SUPPORT

	SetVisibleSurface( (GxVideoSurf *)m_pPrimarySurface );

	// Here, we use EngCreatePalette to create a palette that that MGDI will use as a
	// stock palette

	if( pPalette )
	{
		DEBUGMSG( 0, ( TEXT("CE has passed pPalette non-zero\n") ) );
		DEBUGMSG( 0, ( TEXT("m_pMode->Bpp = %08X\n"), m_pMode->Bpp ) );

		if(m_pMode->Bpp > 8 ) {
			*pPalette = EngCreatePalette
								(
									PAL_BITFIELDS,
									0, 
									NULL,
									BitMasks[0],
									BitMasks[1],
									BitMasks[2]
								);
		} 
		else {
			*pPalette = EngCreatePalette
								(
									PAL_INDEXED,
									PALETTE_SIZE, 	// i.e. 256
									(ULONG *)_rgbIdentity,
									0,
									0,
									0
								);
		}
	}

#ifdef DD_SUPPORT
    // Update video timings based on new display mode
    pDriverData->hTiming  = (WORD)((MEM_READ_32(GXregisters, DC_H_TIMING_1) & 0x07F80000) >> 16);
    pDriverData->hTiming -= (WORD)((MEM_READ_32(GXregisters, DC_H_TIMING_3) & 0x07F80000) >> 16);
    pDriverData->hTiming -= 13;

    pDriverData->vTiming  = (WORD)((MEM_READ_32(GXregisters, DC_V_TIMING_1) & 0x07FF0000) >> 16);
    pDriverData->vTiming -= (WORD)((MEM_READ_32(GXregisters, DC_V_TIMING_3) & 0x07FF0000) >> 16);
    pDriverData->vTiming += 1;

#ifdef TV_NTSC_ENABLE

    //Program the TV specific registers of Dhruva
	//DebugBreak();
	RETAILMSG( 0, ( TEXT("Entering TV mode set code\n") ) );


	WRITE_REG32(CX5530registers, DHRUVA_TVOUT_HORZ_TIMING, tvMode->horz_timing);
	RETAILMSG( 0, ( TEXT("tvMode->horz_timing = %08X\n"), tvMode->horz_timing ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVOUT_HORZ_SYNC, tvMode->horz_sync);
	RETAILMSG( 0, ( TEXT("tvMode->horz_sync = %08X\n"), tvMode->horz_sync ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVOUT_VERT_SYNC, tvMode->vert_sync);
	RETAILMSG( 0, ( TEXT("tvMode->vert_sync = %08X\n"), tvMode->vert_sync ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVOUT_DISP_LINE_END, tvMode->disp_line_end);
	RETAILMSG( 0, ( TEXT("tvMode->disp_line_end = %08X\n"), tvMode->disp_line_end ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVOUT_VERT_DOWN_SCALE, tvMode->vert_down_scale);
	RETAILMSG( 0, ( TEXT("tvMode->vert_down_scale = %08X\n"), tvMode->vert_down_scale ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVOUT_HORZ_SCALE, tvMode->horz_scale);
	RETAILMSG( 0, ( TEXT("tvMode->horz_scale = %08X\n"), tvMode->horz_scale ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVOUT_DEBUG, tvMode->tvout_debug);
	RETAILMSG( 0, ( TEXT("tvMode->tvout_debug = %08X\n"), tvMode->tvout_debug ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVOUT_LINE_SIZE, tvMode->line_size);
	RETAILMSG( 0, ( TEXT("tvMode->line_size = %08X\n"), tvMode->line_size ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_CONTROL1, tvMode->encoder_control1);
	RETAILMSG( 0, ( TEXT("tvMode->encoder_control1 = %08X\n"), tvMode->encoder_control1 ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_CONTROL2, tvMode->encoder_control2);
	RETAILMSG( 0, ( TEXT("tvMode->encoder_control2 = %08X\n"), tvMode->encoder_control2 ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_CONTROL3, tvMode->encoder_control3);
	RETAILMSG( 0, ( TEXT("tvMode->encoder_control3 = %08X\n"), tvMode->encoder_control3 ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_SUBCARRIER_FREQ, tvMode->subcarrier_freq);
	RETAILMSG( 0, ( TEXT("tvMode->subcarrier_freq = %08X\n"), tvMode->subcarrier_freq ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_DISPLAY_POSITION, tvMode->display_position);
	RETAILMSG( 0, ( TEXT("tvMode->display_position = %08X\n"), tvMode->display_position ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_DISPLAY_SIZE, tvMode->display_size);
	RETAILMSG( 0, ( TEXT("tvMode->display_size = %08X\n"), tvMode->display_size ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_CLOSE_CAP_DATA, tvMode->close_cap_data);
	RETAILMSG( 0, ( TEXT("tvMode->close_cap_data = %08X\n"), tvMode->close_cap_data ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_EXTENDED_DATA_SERVICE, tvMode->extended_data_service);
	RETAILMSG( 0, ( TEXT("tvMode->extended_data_service = %08X\n"), tvMode->extended_data_service ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_CGMS_DATA, tvMode->cgms_data);
	RETAILMSG( 0, ( TEXT("tvMode->cgms_data = %08X\n"), tvMode->cgms_data ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_WSS_DATA, tvMode->wss_data);
	RETAILMSG( 0, ( TEXT("tvMode->wss_data = %08X\n"), tvMode->wss_data ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_CLOSE_CAP_CONTROL, tvMode->close_cap_control);
	RETAILMSG( 0, ( TEXT("tvMode->close_cap_control = %08X\n"), tvMode->close_cap_control ) );

	WRITE_REG32(CX5530registers, DHRUVA_TVENCODER_DAC_CONTROL, tvMode->dac_control);
	RETAILMSG( 0, ( TEXT("tvMode->dac_control = %08X\n"), tvMode->dac_control ) );

	WRITE_REG32(CX5530registers, DHRUVA_DISPLAY_MODE, tvMode->display_mode);
    tvtemp = READ_REG32(CX5530registers, DHRUVA_DISPLAY_MODE);
	RETAILMSG( 0, ( TEXT("tvMode->display_mode = %08X\n"), tvtemp ) );

#endif //TV_NTSC_ENABLE
#endif //DD_SUPPORT
	return S_OK;
}