dhruva_regs.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*
 * $Workfile: dhruva_regs.h $
 * $Revision: 2 $
 * $Date: 4/07/00 9:10a $
 * $Modtime: 4/07/00 9:01a $
 * $Author: Sarma $
 *
 * Register addresses associated with the Dhruva/MediaPC.
 *
 * Copyright (c) 1998 National Semiconductor Corporation.
 * All Rights Reserved.
 *
 * This software is the confidential and proprietary information of National 
 * Semiconductor Corporation. ("Confidential Information").
 * You shall not disclose such Confidential Information and shall use it only
 * in accordance with the terms of the license agreement you entered into
 * with National Semiconductor Corporation.
 * This code is supplied as is.
 *
 */

/*
 *$Log: /CE/Platform/Nsc/Drivers/Video/gxvideo/ddraw/dhruva_regs.h $
 * 
 * 2     4/07/00 9:10a Sarma
 * Removed Cyrix Corporation from the legal/confidentail information. Also
 * added for files not containing this info.
 * 
 * 1     3/29/00 9:42a Sarma
 * Adding the initial revision of the directdraw interface.
 * 
 * 1     3/26/00 9:53p Hari
 * Durango based WinCE graphics driver for GXm/5530(gxvideo). This is a
 * beta version of gxvideo with base graphics and directdraw. Used durango
 * v2.1.
 * Tested for CEPC and TVPAK_CEPC on unicorn platform.
 * 
 * 1     3/23/00 10:14p Hari
 * Complete Driver(Base + Ddraw) has been modified to use Durango
 * routines.
 * 
 * 1     3/22/00 11:45a Hari
 * BitBlt part of DirectDraw has been modified using Durango routines.
*/
#ifdef DD_SUPPORT

#ifndef DHRUVA_REGS_H

#define DHRUVA_REGS_H

/**************************************************************************/
// Dhruva/MediaPC registers    - ullas

#define DHRUVA_MISC                             0x28
#define DHRUVA_PLL_CLOCK                        0x2C

#define DHRUVA_VIDEO_DOWNSCALAR_CONTROL         0x3C
#define DHRUVA_VIDEO_DOWNSCALAR_COEFF           0x40
#define DHRUVA_CRC_SIGNATURE                    0x44
#define DHRUVA_CHIP_REVISION_NUMBER             0x48

#define DHRUVA_DISPLAY_MODE                     0x100

#define DHRUVA_TVOUT_HORZ_TIMING                0x800
#define DHRUVA_TVOUT_HORZ_SYNC                  0x804
#define DHRUVA_TVOUT_VERT_SYNC                  0x808
#define DHRUVA_TVOUT_DISP_LINE_END              0x80C
#define DHRUVA_TVOUT_VERT_DOWN_SCALE            0x810
#define DHRUVA_TVOUT_HORZ_SCALE                 0x814
#define DHRUVA_TVOUT_DEBUG                      0x818
#define DHRUVA_TVOUT_LINE_SIZE                  0x81C

#define DHRUVA_TVENCODER_CONTROL1               0xC00
#define DHRUVA_TVENCODER_CONTROL2               0xC04
#define DHRUVA_TVENCODER_CONTROL3               0xC08
#define DHRUVA_TVENCODER_SUBCARRIER_FREQ        0xC0C
#define DHRUVA_TVENCODER_DISPLAY_POSITION       0xC10
#define DHRUVA_TVENCODER_DISPLAY_SIZE           0xC14
#define DHRUVA_TVENCODER_CLOSE_CAP_DATA         0xC18
#define DHRUVA_TVENCODER_EXTENDED_DATA_SERVICE  0xC1C
#define DHRUVA_TVENCODER_CGMS_DATA              0xC20
#define DHRUVA_TVENCODER_WSS_DATA               0xC24
#define DHRUVA_TVENCODER_CLOSE_CAP_CONTROL      0xC28
#define DHRUVA_TVENCODER_DAC_CONTROL            0xC2C


#endif //DHRUVA_REGS_H

#endif //DD_SUPPORT