ioport.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*
 * $Workfile: IOPORT.H $
 * $Revision: 3 $
 * $Date: 4/07/00 8:51a $
 * $Modtime: 4/07/00 8:36a $
 * $Author: Sarma $
 *
 * Copyright (c) 1998 National Semiconductor Corporation.
 * All Rights Reserved.
 *
 * This software is the confidential and proprietary information of National 
 * Semiconductor Corporation. ("Confidential Information").
 * You shall not disclose such Confidential Information and shall use it only
 * in accordance with the terms of the license agreement you entered into
 * with National Semiconductor Corporation.
 * This code is supplied as is.
 *
 */

/*
 *$Log: /CE/Platform/Nsc/Drivers/Video/gxvideo/base/IOPORT.H $
 * 
 * 3     4/07/00 8:51a Sarma
 * Removed Cyrix Corporation from the legal/confidentail information.
 * 
 * 2     11/12/98 3:14p Sarma
 * Added Confidential copyright to files with VSS keywords for
 * log/history.
 *$History: IOPORT.H $
 * 
 * *****************  Version 3  *****************
 * User: Sarma        Date: 4/07/00    Time: 8:51a
 * Updated in $/CE/Platform/Nsc/Drivers/Video/gxvideo/base
 * Removed Cyrix Corporation from the legal/confidentail information.
 * 
 * *****************  Version 2  *****************
 * User: Sarma        Date: 11/12/98   Time: 3:14p
 * Updated in $/wince/v2.1/gxvideo
 * Added Confidential copyright to files with VSS keywords for
 * log/history.
*/

#ifndef __IOPORT_H__
#define __IOPORT_H__

#include <wdm.h>

// Type conversions from Port to derived types
#define PORT_WO_8 *(WOPort8 *)&
#define PORT_RO_8 *(ROPort8 *)&
#define PORT_RW_8 *(RWPort8 *)&
#define PORT_WO_16 *(WOPort16 *)&
#define PORT_RO_16 *(ROPort16 *)&
#define PORT_RW_16 *(RWPort16 *)&
#define MM_RO_16 *(ROReg16 *)&
#define MM_RW_16 *(RWReg16 *)&
#define MM_WO_16 *(WOReg16 *)&
#define MM_WO_32 *(WOReg32 *)&

// Sample usage:
// #define reg_TST_WO           (PORT_WO_8 m_Port[PortId_3DA])
// #define reg_TST_RO           (PORT_RO_8 m_Port[PortId_3DA])
// #define reg_TST_RW           (PORT_RW_8 m_Port[PortId_3DA])

#define PORT_RANGE_SIZE 4096
struct PortRange
{
    PortRange                       *m_pNextRange;
    unsigned short          m_nFirstPortNo;
    unsigned char           *m_nPortBase;
};

class Port
{
protected:
    unsigned char * m_pPort;
public:
    void Map( unsigned short port, PortRange * &pFirstRange );
};

class WOPort8 : public Port
{
public:
    unsigned char operator =(unsigned char v)
    {
        WRITE_PORT_UCHAR( (PUCHAR)m_pPort, v );
        return v;
    }
};

class ROPort8 : public Port
{
public:
    operator unsigned char()
    {
        return READ_PORT_UCHAR( (PUCHAR)m_pPort );
    }
};

class RWPort8 : public Port
{
public:
    unsigned char operator =(unsigned char v)
    {
        WRITE_PORT_UCHAR( (PUCHAR)m_pPort, v );
        return v;
    }
    operator unsigned char()
    {
        return READ_PORT_UCHAR( (PUCHAR)m_pPort );
    }
};

class RWSplitPort8
{
private:
    Port    *m_pReadPort;
    Port *m_pWritePort;
public:
    void Init( Port &readPort, Port &writePort )
    {
        m_pReadPort = &readPort;
        m_pWritePort = &writePort;
    }
    unsigned char operator =(unsigned char v)
    {
        return (PORT_WO_8 (*m_pWritePort)) = v;
    }
    operator unsigned char()
    {
        return (PORT_RO_8 (*m_pReadPort));
    }
};

class WOPort16 : public Port
{
public:
    unsigned short operator =(unsigned short v)
    {
        WRITE_PORT_USHORT( (PUSHORT)m_pPort, v );
        return v;
    }
};

class ROPort16 : public Port
{
public:
    operator unsigned short()
    {
        return READ_PORT_USHORT( (PUSHORT)m_pPort );
    }
};

class RWPort16 : public Port
{
public:
    unsigned short operator =(unsigned short v)
    {
        WRITE_PORT_USHORT( (PUSHORT)m_pPort, v );
        return v;
    }
    operator unsigned short()
    {
        return READ_PORT_USHORT( (PUSHORT)m_pPort );
    }
};

class IndexedReg8
{
private:
    RWPort8 *m_pAddressPort;
    RWPort8 *m_pDataPort;
public:
    void Init( RWPort8 &m_regAddress, RWPort8 &m_regData )
    {
        m_pAddressPort = &m_regAddress;
        m_pDataPort = &m_regData;
    }
    RWPort8& operator [](int nSubscript)
    {
        *m_pAddressPort = (unsigned char)nSubscript;
        return *m_pDataPort;
    }
};


class FlipIndexedReg8
{
private:
    RWPort8 *m_pRWPort;                     // Write addr or data here, read addr here
    ROPort8 *m_pReadDataPort;       // Read data here
    ROPort8 *m_pResetPort;          // Read here to set m_pRWPort[writes] to addr
    RWSplitPort8 m_regData;         // Points to RWPort for writes, and ReadDataPort for reads
public:
    void ResetToAddr()
    {
        // Set m_pRWPort[writes] to addr
        volatile unsigned char temp = *m_pResetPort;
    }
    void Init( Port &rwPort, Port &readDataPort, Port &resetPort )
    {
        m_pRWPort = &(PORT_RW_8 rwPort);
        m_pReadDataPort = &(PORT_RO_8 readDataPort);
        m_regData.Init( readDataPort, rwPort ); 
        m_pResetPort = &(PORT_RO_8 resetPort);
    }
    RWSplitPort8& operator [](int nSubscript)
    {
        ResetToAddr();
        *m_pRWPort = (unsigned char)nSubscript;
        return m_regData;
    }
};


class SubIndexedReg16
{
private:
    volatile unsigned short *m_pMMReg;
    unsigned short m_nRegId;
public:
    void Init( unsigned short *pMMReg, unsigned short regNo )
    {
        m_pMMReg = pMMReg;
        m_nRegId = regNo<<12;
    }
    operator unsigned short()
    {
        *m_pMMReg = 0xF000 | (m_nRegId>>12);
        return 0x0FFF & *m_pMMReg;
    }
    unsigned short operator =(unsigned short v)
    {
        *m_pMMReg = v | m_nRegId;
        return v;
    }
};


class SubIndexedRegArray16
{
private:
    unsigned short *m_pMMReg;               // Address used for reads & writes
    SubIndexedReg16 m_aSubReg[16];
public:
    void Init( unsigned short *pMMReg )
    {
        int i;
        for( i=0; i<16; i++ )
            m_aSubReg[i].Init( pMMReg, i);
    }

    SubIndexedReg16& operator [](int nSubscript)
    {
        return m_aSubReg[nSubscript];
    }
};

class RWReg16
{
private:
    volatile unsigned short m_nV;
public:
    unsigned short operator =(unsigned short v)
    {
        m_nV = v;
        return v;
    }
    operator unsigned short()
    {
        return m_nV;
    }
};

class ROReg16
{
private:
    volatile unsigned short m_nV;
public:
    operator unsigned short()
    {
        return m_nV;
    }
};

class WOReg16
{
private:
    volatile unsigned short m_nV;
public:
    unsigned short operator =(unsigned short v)
    {
        m_nV = v;
        return v;
    }
};

class WOReg32
{
private:
    volatile unsigned long m_nV;
public:
    unsigned long operator =(unsigned long v)
    {
        m_nV = v;
        return v;
    }
};

#endif // __IOPORT_H__