📄 gpevga.cpp
字号:
0x041F031F, 0x041f031f, 0x037f032f, 0x037f032f, 1,// horizontal timings
0x02700257, 0x02700257, 0x025b0258, 0x025b0258, 1,// vertical timings
0x37D8D802 // CX5530 = 80.000 MHz
},
//
// LCD TURNON
{ { 4, 1024, 768, 8, 60, gpe8Bpp }, // mode#0: 640 x 480 8Bpp 60Hz VESA mode 0x101
1024, 768, 8, 60, // display parameters
0x00006583, 0x0000006F, 0x00003005, // gcfg, tcfg, ocfg
0x00000000, 0x000C0000, 0x001FFF00, // memory organization
0x00100100, 0x00000080, // line delta, buffer size
0x053F03FF, 0x053F03FF, 0x049F0417, 0x049F0417, 1,// horizontal timings
0x032502FF, 0x032502FF, 0x03080302, 0x03080302, 1,// vertical timings
0x37911801 // CX5530 = 65.000 MHz
},
{ { 0, 1024, 768, 8, 75, gpe8Bpp }, // mode#0: 640 x 480 8Bpp 60Hz VESA mode 0x101
1024, 768, 8, 75, // display parameters
0x00006583, 0x0000006F, 0x00003005, // gcfg, tcfg, ocfg
0x00000000, 0x000C0000, 0x001FFF00, // memory organization
0x00040100, 0x00000080, // line delta, buffer size
0x051F03FF, 0x051F03FF, 0x046F040F, 0x046F040F, 1,// horizontal timings
0x031F02FF, 0x031F02FF, 0x03030300, 0x03030300, 1,// vertical timings
0x27915801 // CX5530 = 75.000 MHz
},
{ { 6, 1280, 1024, 8, 60, gpe8Bpp}, // mode#0: 1280 x 1024 8Bpp 60Hz VESA mode 0x111
1280, 1024, 8, 60, // display parameters
0x00006583, 0x0000006F, 0x00003005, // gcfg, tcfg, ocfg
0x00000000, 0x00000500, 0x001FFF00, // memory organization fb_start, cb_start, cur_start
0x00200200, 0x000000A0, // line delta, buffer size
0x069F04FF, 0x06970507, 0x05BF053F, 0x05BF053F, 1,// horizontal timings
0x042903FF, 0x042903FF, 0x04030400, 0x04030400, 1,// vertical timings
0x2710C805 // CX5530 = 108.00 MHz
},
{ { 7, 1280, 1024, 8, 75, gpe8Bpp}, // mode#0: 1280 x 1024 8Bpp 75Hz VESA mode 0x111
1280, 1024, 8, 75, // display parameters
0x00006583, 0x0000006F, 0x00003005, // gcfg, tcfg, ocfg
0x00000000, 0x00000500, 0x001FFF00, // fb_start, cb_start, cur_start
0x00200200, 0x000000A0, // line delta, buffer size
0x069704FF, 0x069704FF, 0x059F050F, 0x059F050F, 1,// horizontal timings
0x042903FF, 0x042903FF, 0x04030400, 0x04030400, 1,// vertical timings
0x27316803 // CX5530 = 135.00 MHz
}
#endif
};
#ifdef DD_SUPPORT
TVMODE TvParams[NUMBEROFTVMODES] = {
{
0x00790359, //horz_timing;
0x03580350, //horz_sync;
0x0A002001, //vert_sync;
0x039C00F0, //disp_line_end;
0xFFFFFFFF, //vert_down_scale;
0x10220700, //horz_scale;
0x00000008, //tvout_debug;
0x0002D0F0, //emma_bypass;
0xA2E03000, //encoder_control1;
0x1FF20000, //encoder_control2;
0x00000000, //encoder_control3;
0x21F0AAAA, //subcarrier_freq;
0x00030071, //display_position;
0x00EF02CF, //display_size;
0x00000000, //close_cap_data;
0x00000000, //ext_data_service;
0x00000000, //cgms_data;
0x00000000, //wss_data;
0x00000000, //close_cap_control;
0x00000000, //dac_control;
0x00000000 //display_mode;
},
{
0x00790359, //horz_timing;
0x03580350, //horz_sync;
0x0A002001, //vert_sync;
0x039C00F0, //disp_line_end;
0xFFFFFFFF, //vert_down_scale;
0x10220700, //horz_scale;
0x00000008, //tvout_debug;
0x0002D0F0, //emma_bypass;
0xA2E03000, //encoder_control1;
0x1FF20000, //encoder_control2;
0x00000000, //encoder_control3;
0x21F12000, //subcarrier_freq;
0x00030071, //display_position;
0x00EF02CF, //display_size;
0x00000000, //close_cap_data;
0x00000000, //ext_data_service;
0x00000000, //cgms_data;
0x00000000, //wss_data;
0x00000000, //close_cap_control;
0x00000000, //dac_control;
0x00000000 //display_mode;
}
};
#endif //DD_SUPPORT
INSTANTIATE_MODE_INIT
GPEVGA::GPEVGA()
{
DEBUGMSG( 1,(TEXT("GPEVGA::GPEVGA\r\n")));
m_pPortRanges = (PortRange *)NULL;
// Reserve / Map in - standard VGA ports
m_VGAIOPort[PortId_3BA].Map(0x3BA, m_pPortRanges );
m_VGAIOPort[PortId_3C0].Map(0x3C0, m_pPortRanges );
m_VGAIOPort[PortId_3C1].Map(0x3C1, m_pPortRanges );
m_VGAIOPort[PortId_3C2].Map(0x3C2, m_pPortRanges );
m_VGAIOPort[PortId_3C3].Map(0x3C3, m_pPortRanges );
m_VGAIOPort[PortId_3C4].Map(0x3C4, m_pPortRanges );
m_VGAIOPort[PortId_3C5].Map(0x3C5, m_pPortRanges );
m_VGAIOPort[PortId_3C6].Map(0x3C6, m_pPortRanges );
m_VGAIOPort[PortId_3C7].Map(0x3C7, m_pPortRanges );
m_VGAIOPort[PortId_3C8].Map(0x3C8, m_pPortRanges );
m_VGAIOPort[PortId_3C9].Map(0x3C9, m_pPortRanges );
m_VGAIOPort[PortId_3CA].Map(0x3CA, m_pPortRanges );
m_VGAIOPort[PortId_3CC].Map(0x3CC, m_pPortRanges );
m_VGAIOPort[PortId_3CE].Map(0x3CE, m_pPortRanges );
m_VGAIOPort[PortId_3CF].Map(0x3CF, m_pPortRanges );
m_VGAIOPort[PortId_3D4].Map(0x3D4, m_pPortRanges );
m_VGAIOPort[PortId_3D5].Map(0x3D5, m_pPortRanges );
m_VGAIOPort[PortId_3DA].Map(0x3DA, m_pPortRanges );
// Initialize access to registers which have different read ports from write ports
DEBUGMSG( 1,(TEXT("Initialize access to registers\r\n")));
reg_MISC.Init( m_VGAIOPort[PortId_3CC], m_VGAIOPort[PortId_3C2] );
reg_FCR_WT.Init( m_VGAIOPort[PortId_3CA], m_VGAIOPort[PortId_3DA] );
// Initialize access to indexed ranges of registers
DEBUGMSG( 1,(TEXT("Initialize access to indexed ranges of registers\r\n")));
DEBUGMSG( 1,(TEXT("Initialize access to SR[]\r\n")));
reg_SR.Init( reg_SR_ADDR, reg_SR_DATA );
DEBUGMSG( 1,(TEXT("Initialize access to CR[]\r\n")));
reg_CR.Init( reg_CR_ADDR, reg_CR_DATA );
DEBUGMSG( 1,(TEXT("Initialize access to GR[]\r\n")));
reg_GR.Init( reg_GR_ADDR, reg_GR_DATA );
DEBUGMSG( 1,(TEXT("Initialize access to AR[]\r\n")));
reg_AR.Init( reg_AR_ADDR, reg_AR_DATA, reg_AR_RESET );
}
void GPEVGA::SetVGAMode( DISPLAYMODE *pMode )
{
DEBUGMSG( 1,(TEXT("GPEVGA::SetVGAMode\r\n")));
DEBUGMSG( 1,(TEXT("Leaving GPEVGA::SetVGAMode\r\n")));
}
void GPEVGA::DetermineScreenRefreshRate()
{
DEBUGMSG( 1,(TEXT("GPEVGA::DetermineScreenRefreshRate\r\n")));
//WaitForVBlank();
int i;
unsigned long startTickCount = GetTickCount();
for( i=0; i<20; i++ );
//WaitForVBlank();
m_nTicksPerFrame = ( GetTickCount() - startTickCount + 10 ) / 20;
DEBUGMSG( 1, ( TEXT("Frame takes %d ticks\r\n"), m_nTicksPerFrame ));
}
int GPEVGA::InVBlank()
{
return reg_STATUS_1 & 0x08;
}
void GPEVGA::WaitForVBlank()
{
unsigned long i;
// First wait to be out of vblank
for (i = 0; i < 0x1000000; i++)
if( !(reg_STATUS_1 & 0x08 ) )
break;
// Wait to get into vblank
for (; i < 0x1000000; i++)
if( reg_STATUS_1 & 0x08 )
break;
VBlankReceived(); // Reset counters etc
}
void GPEVGA::LockVGA()
{
DEBUGMSG( 1,(TEXT("GPEVGA::LockVGA\r\n")));
// disable writes to CR0..7
reg_VRE = reg_VRE | 0x80; // reg_CR[0x11]
}
void GPEVGA::UnlockVGA()
{
DEBUGMSG( 1,(TEXT("GPEVGA::UnlockVGA\r\n")));
// enable writes to CR0..7
reg_VRE = reg_VRE & 0x7F; // reg_CR[0x11]
}
SCODE GPEVGA::SetPalette(
const PALETTEENTRY *src,
unsigned short firstEntry,
unsigned short numEntries )
{
unsigned long entry;
DEBUGMSG( 0,(TEXT("GPEVGA::SetPalette\r\n")));
Unlock();
DISPLAYMODE *DpyParams = GetDisplayParams(GetModeId());
if(DpyParams->bpp == 8) {
if( firstEntry < 0 || firstEntry + numEntries > 256 )
return E_INVALIDARG;
for( ; numEntries; numEntries-- )
{
WRITE_REG32(GXregisters, DC_PAL_ADDRESS, firstEntry++);
entry = 0;
entry = ((src->peBlue & 0xFF)>>2) |
(((src->peGreen & 0xFF)>>2) << 6) |
(((src->peRed & 0xFF)>>2) << 12);
src++;
WRITE_REG32(GXregisters, DC_PAL_DATA, entry);
}
}
// CURSOR COLORS ARE LOCATED AT x100 AND x101 ARE EXTENSIONS TO THE
// NORMAL 256 COLORTABLE FOR CURSOR 0 AND 1 EXPANSION COLORS. WHERE THE
// 0 EXPANSION COLOR IS BLACK AND THAT OF 1 IS WHITE BY DEFAULT.
WRITE_REG32(GXregisters, DC_PAL_ADDRESS, 0x100);
WRITE_REG32(GXregisters, DC_PAL_DATA, 0);
WRITE_REG32(GXregisters, DC_PAL_ADDRESS, 0x101);
WRITE_REG32(GXregisters, DC_PAL_DATA, 0x3ffff);
#if 0
{
unsigned long addr, data;
addr = 0x101;
WRITE_REG32(GXregisters, DC_PAL_ADDRESS, addr );
DEBUGMSG( 1, ( TEXT("PAL ADDR = %08X\r\n" ), addr ) );
data = READ_REG32(GXregisters, DC_PAL_DATA );
DEBUGMSG( 1, ( TEXT("PAL DATA = %08X\r\n" ), data ) );
}
#endif
Lock();
return S_OK;
}
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