gpevga.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*
 * $Workfile: GPEVGA.H $
 * $Revision: 7 $
 * $Date: 4/07/00 8:50a $
 * $Modtime: 4/07/00 8:37a $
 * $Author: Sarma $
 *
 * Copyright (c) 1998 National Semiconductor Corporation.
 * All Rights Reserved.
 *
 * This software is the confidential and proprietary information of National 
 * Semiconductor Corporation. ("Confidential Information").
 * You shall not disclose such Confidential Information and shall use it only
 * in accordance with the terms of the license agreement you entered into
 * with National Semiconductor Corporation.
 * This code is supplied as is.
 *
 */

/*
 *$Log: /CE/Platform/Nsc/Drivers/Video/gxvideo/base/GPEVGA.H $
 * 
 * 7     4/07/00 8:50a Sarma
 * Removed Cyrix Corporation from the legal/confidentail information.
 * 
 * 6     3/29/00 9:32a Sarma
 * Added New structure for TVout numbers in mode setting, The 640x480 and
 * 800x600 for 16 bit are changed as per bSqure driver, do we really need
 * it - jatinder.
 * 
 * 5     9/14/99 11:25a Sarma
 * Use appropraite Horiz/Vert Sync polarity as per the VESA document
 * "Monitor Timing Specifications V1.0 Rev 0.8". Now we have a seperate
 * filed in each resolution data having this information, which will be
 * used in setmode.
 * 
 * 4     8/11/99 4:15p Sarma
 * Added support for 85Hx resoulution for 640x480, 800x600, 1024x768.
 * 1280x1024 dosen't support 85Hz as it is not sable.
 * 
 * 3     11/13/98 11:32a Sarma
 * 85 Hz needs to be removed as its not being supported.
 * 
 * 2     11/12/98 3:27p Sarma
 * Added Confidential copyright to files with VSS keywords for
 * log/history.
 * Added mode identification tags for those modes likely to be used.
 *$History: GPEVGA.H $
 * 
 * *****************  Version 7  *****************
 * User: Sarma        Date: 4/07/00    Time: 8:50a
 * Updated in $/CE/Platform/Nsc/Drivers/Video/gxvideo/base
 * Removed Cyrix Corporation from the legal/confidentail information.
 * 
 * *****************  Version 6  *****************
 * User: Sarma        Date: 3/29/00    Time: 9:32a
 * Updated in $/CE/Platform/Nsc/Drivers/Video/gxvideo/base
 * Added New structure for TVout numbers in mode setting, The 640x480 and
 * 800x600 for 16 bit are changed as per bSqure driver, do we really need
 * it - jatinder.
 * 
 * *****************  Version 5  *****************
 * User: Sarma        Date: 9/14/99    Time: 11:25a
 * Updated in $/wince/v2.1/gxvideo
 * Use appropraite Horiz/Vert Sync polarity as per the VESA document
 * "Monitor Timing Specifications V1.0 Rev 0.8". Now we have a seperate
 * filed in each resolution data having this information, which will be
 * used in setmode.
 * 
 * *****************  Version 4  *****************
 * User: Sarma        Date: 8/11/99    Time: 4:15p
 * Updated in $/wince/v2.1/gxvideo
 * Added support for 85Hx resoulution for 640x480, 800x600, 1024x768.
 * 1280x1024 dosen't support 85Hz as it is not sable.
 * 
 * *****************  Version 3  *****************
 * User: Sarma        Date: 11/13/98   Time: 11:32a
 * Updated in $/wince/v2.1/gxvideo
 * 85 Hz needs to be removed as its not being supported.
 * 
 * *****************  Version 2  *****************
 * User: Sarma        Date: 11/12/98   Time: 3:27p
 * Updated in $/wince/v2.1/gxvideo
 * Added Confidential copyright to files with VSS keywords for
 * log/history.
 * Added mode identification tags for those modes likely to be used.
*/

#ifndef __GPEVGA_H__
#define __GPEVGA_H__

#include "ioport.h"     // definitions of the port classes used here

//Number of supported Display Modes
#define NUMBEROFMODES   52

#define DHRUVA_MISC_DATA    0x00001001

#ifdef FB16BPP
#define DHRUVA_PLL_CLOCK_DATA 0x0010170c
#else
#define DHRUVA_PLL_CLOCK_DATA 0x0050600C
#endif


#ifdef DD_SUPPORT
#define NUMBEROFTVMODES 2
struct TVMODE;
#endif //DD_SUPPORT

struct DISPLAYMODE;
class GPEVGA;

//
// Class GPEVGA
//
// The GPEVGA class is intended to ease the development of GPE device drivers for
// graphics cards based on VGA. Classes for SVGA devices can be derived from the
// GPEVGA class which takes care of VGA configuration and provides a number of useful
// register mappings to make the remainder of the class definition relatively easy.
//
// Note that this is a base class and contains pure virtual functions which must be
// implemented for derived concrete classes


// List of I/O ports which are used to access standard VGA registers
enum EVGAPortIDs{
    PortId_3BA,
    PortId_3C0,
    PortId_3C1,
    PortId_3C2,
    PortId_3C3,
    PortId_3C4,
    PortId_3C5,
    PortId_3C6,
    PortId_3C7,
    PortId_3C8,
    PortId_3C9,
    PortId_3CA,
    PortId_3CC,
    PortId_3CE,
    PortId_3CF,
    PortId_3D4,
    PortId_3D5,
    PortId_3DA,
    numVGAPortIDs
};

#ifdef DD_SUPPORT
class GPEVGA : public DDGPE
#else
class GPEVGA : public GPE
#endif //DD_SUPPORT
{
protected:
    PortRange       *m_pPortRanges;         // Required for ioport.h
    Port            m_VGAIOPort[numVGAPortIDs];   // All IO ports used by VGA
    RWSplitPort8    reg_MISC;               // R:3CC,W:3C2 Miscellaneous output register
    RWSplitPort8    reg_FCR_WT;             // R:3CA,W:3DA Feature control register
    IndexedReg8     reg_SR;                 // Sequence registers
    IndexedReg8     reg_CR;                 // CRTC registers (and extensions)
    IndexedReg8     reg_GR;                 // Graphics controller registers
    FlipIndexedReg8 reg_AR;                 // Attribute controller registers
    unsigned int    m_nTicksPerFrame;       // E.g. 17 for 60 Hz frames, 1mS ticks
    int             m_nXHot;                // Hot spot for cursor
    int             m_nYHot;
    unsigned char   *GXregisters;           // pointer to GX registers
    unsigned char   *CX5530registers;       // pointer to CX5530 registers
    void            Unlock();
    void            Lock();
    unsigned long   m_unlock;
public:
                    GPEVGA();               // Maps in standard VGA ports
    void            SetVGAMode( DISPLAYMODE *pMode );
    virtual void    WaitForVBlank();
    void            DetermineScreenRefreshRate();
    virtual int     InVBlank();
    void            UnlockVGA();
    void            LockVGA();
    virtual SCODE   SetPalette(
                        const PALETTEENTRY *src,
                        unsigned short firstEntry,
                        unsigned short numEntries );
    virtual void    VBlankReceived() = 0;   // Called when VBlank is entered
};

//---------------------------------------------------------------------------
// VIDEO MODE TABLES:
//
// The following structure is used to conatain the information used when 
// setting the various display modes.
//

struct DISPLAYMODE
{
    GPEMode  gpeMode;

    // DISPLAY MODE PARAMETERS

    int xres;
    int yres;
    int bpp;
    int hz;

    // VALUES USED TO SET THE GX DISPLAY CONTROLLER

    unsigned long gcfg;
    unsigned long tcfg;
    unsigned long ocfg;
    unsigned long fb_offset; 
    unsigned long cb_offset; 
    unsigned long curs_offset; 
    unsigned long line_delta;
    unsigned long buffer_size;
    unsigned long htiming1;
    unsigned long htiming2;
    unsigned long htiming3;
    unsigned long fp_htiming;
    unsigned char hsync_pol;
    unsigned long vtiming1;
    unsigned long vtiming2;
    unsigned long vtiming3;
    unsigned long fp_vtiming;
    unsigned char vsync_pol;

    // VALUES USED TO SET CLOCK FREQUENCY FOR THE CX5530 

    unsigned long cx5520_clock;
    unsigned long cx5530_clock;
    unsigned long cx55xx_clock;

};

#ifdef DD_SUPPORT
struct TVMODE
{
    // VALUES USED TO SET THE DHRUVA TV CONTROLLER
    unsigned long horz_timing;
    unsigned long horz_sync;
    unsigned long vert_sync;
    unsigned long disp_line_end; 
    unsigned long vert_down_scale; 
    unsigned long horz_scale; 
    unsigned long tvout_debug;
    unsigned long line_size;
    unsigned long encoder_control1;
    unsigned long encoder_control2;
    unsigned long encoder_control3;
    unsigned long subcarrier_freq;
    unsigned long display_position;
    unsigned long display_size;
    unsigned long close_cap_data;
    unsigned long extended_data_service;
    unsigned long cgms_data;
    unsigned long wss_data;
    unsigned long close_cap_control;
    unsigned long dac_control;
    unsigned long display_mode;
};
#endif //DD_SUPPORT

enum NUM_MODES {
    DDI_640x480x8x60=0,
    DDI_640x480x16x60,
    DDI_640x480x8x72,
    DDI_640x480x16x72,
    DDI_640x480x8x75,
    DDI_640x480x8x85,
    DDI_640x480x16x75,
    DDI_640x480x16x85,
    DDI_800x600x8x60,
    DDI_800x600x16x60,
    DDI_800x600x8x72,
    DDI_800x600x16x72,
    DDI_800x600x8x75,
    DDI_800x600x8x85,
    DDI_800x600x16x75,
    DDI_800x600x16x85,
    DDI_1024x768x8x60,
    DDI_1024x768x16x60,
    DDI_1024x768x8x70,
    DDI_1024x768x16x70,
    DDI_1024x768x8x75,
    DDI_1024x768x8x85,
    DDI_1024x768x16x75,
    DDI_1024x768x16x85,
    DDI_1280x1024x8x60,
    DDI_1280x1024x8x75,
    //DDI_640x480x8x76,     //for flat panel
    //DDI_800x600x8x76,     //for flat panel
#ifdef DD_SUPPORT
    DDI_TV_PAL,             //for PAL TV - ullas
    DDI_TV_NTSC,            //for NTSC TV
#endif //DD_SUPPORT
    numVGAmodes,
    DDI_NOT_SUPPORTED
};

#ifdef DD_SUPPORT
extern TVMODE TvParams[];
#endif //DD_SUPPORT

extern DISPLAYMODE DisplayParams[];
extern int          DpyModeExists(int);
extern DISPLAYMODE* GetDisplayParams(int);


// Direct access IO mapped registers

#define reg_AR_ADDR         (PORT_RW_8 m_VGAIOPort[PortId_3C0 ]) //Select AR0..14.  On Writes, sets 3C0[write]->ATR_DATA
#define reg_AR_DATA         (PORT_RW_8 m_VGAIOPort[PortId_3C1 ]) //Read/Write AR0..14 On Writes, sets 3C0[write]->ATR_AD
#define reg_AR_RESET        (PORT_RO_8 m_VGAIOPort[PortId_3BA ]) //Reset flip flop to set3CO[write]->ATR_AD
#define reg_CR_ADDR         (PORT_RW_8 m_VGAIOPort[PortId_3D4 ]) //Select CR0..CR24
#define reg_CR_DATA         (PORT_RW_8 m_VGAIOPort[PortId_3D5 ]) //Read/Write CR0..CR24
#define reg_DAC_DATA        (PORT_RW_8 m_VGAIOPort[PortId_3C9 ]) //Access palette entry (use 3 times)
#define reg_DAC_WR_AD       (PORT_WO_8 m_VGAIOPort[PortId_3C8 ]) //Write index into palette (auto-incr)
#define reg_DAC_AD_MK       (PORT_RW_8 m_VGAIOPort[PortId_3C6 ]) //Pixel read mask (put FF here!)
#define reg_GR_ADDR         (PORT_RW_8 m_VGAIOPort[PortId_3CE ]) //Select GR0..8
#define reg_GR_DATA         (PORT_RW_8 m_VGAIOPort[PortId_3CF ]) //Access GR0..8
#define reg_SR_ADDR         (PORT_RW_8 m_VGAIOPort[PortId_3C4 ]) //Select SR0..18
#define reg_SR_DATA         (PORT_RW_8 m_VGAIOPort[PortId_3C5 ]) //Read/Write SR0..18
#define reg_STATUS_0        (PORT_RO_8 m_VGAIOPort[PortId_3C2 ]) //CRT Irq Pending
#define reg_STATUS_1        (PORT_RO_8 m_VGAIOPort[PortId_3DA ]) //VSync Status


// Indexed registers and their aliases

#define reg_RST_SYNC        reg_SR[0x0]     //  R/W reset - UNUSED!
#define reg_UNLK_EXSR       reg_SR[0x8]     //  R/W Enable SR9..SR18
#define reg_STA_H           reg_CR[0xC]     //  R/W Start addr high
#define reg_STA_L           reg_CR[0xD]     //  R/W Start addr low
#define reg_VRE             reg_CR[0x11]    //  R/W Vertical retrace end
#define reg_COLOR_CMP4Bpp   reg_GR[0x2]     //  R/W Color compare for read mode 1 



#endif // __GPEVGA_H__