init.c

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C语言 代码 · 共 539 行 · 第 1/2 页

   ulReturn = HalGetBusDataByOffset(PNPISAConfiguration,
      0, (nCSN << 8) | nLogicalDevice, &PnPResources, 1,
      sizeof(PnPResources));
   
   if (ulReturn == 0) {
      DEBUGMSG(ZONE_PDD, (TEXT("PCMCIA: Couldn't read resources\r\n")));
      return FALSE;
   }
   
   DEBUGMSG(ZONE_PDD, (TEXT("After Reading 1st.\r\n")));
   
   if (!(PnPResources.Flags & ISA_PNP_RESOURCE_FLAG_ACTIVE))
   {
      //
      // Need to set the resources and activate the device
      //
      
      DEBUGMSG(ZONE_PDD, (TEXT("Setup the resources\r\n")));
      PnPResources.IoPortDescriptors[0] = (USHORT) IoBase;
      
      PnPResources.IRQDescriptors[0].IRQLevel = Irq;
      PnPResources.IRQDescriptors[0].IRQType = 0;
      PnPResources.Flags = ISA_PNP_RESOURCE_FLAG_ACTIVE;
   }      
   
   ulReturn = HalSetBusDataByOffset(PNPISAConfiguration,
       0, (nCSN << 8) | nLogicalDevice, &PnPResources, 1,
       sizeof(PnPResources));
      
   if (ulReturn == 0)
   {
      DEBUGMSG(ZONE_PDD, (TEXT("PCMCIA: Error writing resources\r\n")));
      return FALSE;
   }
      
   ulReturn = HalGetBusDataByOffset(PNPISAConfiguration,
      0, (nCSN << 8) | nLogicalDevice, &PnPResources, 1,
      sizeof(PnPResources));
    
   if (ulReturn == 0)
   {
      DEBUGMSG(ZONE_PDD, (TEXT("PCMCIA: Couldn't read resources\r\n")));
      return FALSE;
   }
      
     
   return TRUE;
}

//
// The PCMCIA MDD calls PDCardInitServices to initialize the PDD layer.
//
STATUS
PDCardInitServices()
{
    UINT8 tmp;
    DWORD IoBase;
    DWORD IoLen;
    DWORD SysIntr;
    DWORD dwRet;

    if ((dwRet = GetRegistryConfig(PCMCIA_DRIVER_KEY, &SysIntr, &IoBase, &IoLen))
        != ERROR_SUCCESS) {
        DEBUGMSG(ZONE_PDD,
            (TEXT("PDCardInitServices GetRegistryConfig failed %d\r\n"),
            dwRet));
        return CERR_GENERAL_FAILURE;
    }

    //
    // On CEPC, one IRQ is used for both the "SYSINTR_PCMCIA_STATE" and 
    // "SYSINTR_PCMCIA_LEVEL" interrupts.
    //
    gIntrPcmciaState = gIntrPcmciaLevel = SysIntr;

    g_Irq = PCMCIA_IRQ;
    private_InitPnP(IoBase, g_Irq);

    //
    // 0x3E0 is the standard Intel compatible socket controller I/O port.
    // The Vadem VG-469 defaults to 0x3E2 !!!
    //
    if (GetIOPorts(IoBase, IoLen)) {
        if (!IsValidPCICSig()) {
            IoBase += 2;    // SCM wants to use 0x3E2 (and now Simple Technology OEMs SCM's)
            if (GetIOPorts(IoBase, IoLen)) {
                if (!IsValidPCICSig()) {
                    return CERR_BAD_ADAPTER;
                }
            } else {
                return CERR_OUT_OF_RESOURCE;
            }
        }

    } else {
        return CERR_OUT_OF_RESOURCE;
    }

DEBUGMSG(ZONE_PDD,
    (TEXT("PDCardInitServices g_PCICIndex = 0x%x, g_PCICData = 0x%x\r\n"),
    g_PCICIndex, g_PCICData));

    InitializeCriticalSection(&g_PCIC_Crit);

    InitSocketNoCard(0);
    InitSocketNoCard(1);

    PCICIndex(0, REG_CHIP_REVISION);
    tmp = PCICDataRead();
DEBUGMSG(ZONE_PDD, (TEXT("PDCardInitServices REG_CHIP_REVISION = 0x%x\r\n"), tmp));

#ifdef DEBUG
    DumpSocketRegisters(0);
    DumpSocketRegisters(1);
#endif

    return CERR_SUCCESS;
}

//
// Function to set the PCIC index register
//
VOID
PCICIndex(
    UINT socket_num,
    UINT8  register_num
    )
{
    WRITE_PORT_UCHAR(g_PCICIndex,
        (UINT8)((socket_num == 0 ? 0 : 0x40)|register_num));
    READ_PORT_UCHAR((PUCHAR)0x61); // I/O delay
}

//
// Function to write to the PCIC data register
//
VOID
PCICDataWrite(
    UINT8 value
    )
{
    WRITE_PORT_UCHAR(g_PCICData, value);
    READ_PORT_UCHAR((PUCHAR)0x61); // I/O delay
}

//
// Function to read the PCIC data register
//
UINT8
PCICDataRead(VOID)
{
    return READ_PORT_UCHAR(g_PCICData);
}

#ifdef DEBUG
UCHAR SocketRegisters[2][REG_LAST_INDEX+1];

LPWSTR RegisterNames[] = {
TEXT("REG_CHIP_REVISION"), //                    0x00
TEXT("REG_INTERFACE_STATUS"), //                 0x01
TEXT("REG_POWER_CONTROL"), //                    0x02
TEXT("REG_INTERRUPT_AND_GENERAL_CONTROL"), //    0x03
TEXT("REG_CARD_STATUS_CHANGE"), //               0x04
TEXT("REG_STATUS_CHANGE_INT_CONFIG"), //         0x05
TEXT("REG_WINDOW_ENABLE"), //                    0x06
TEXT("REG_IO_WINDOW_CONTROL"), //                0x07
TEXT("REG_IO_MAP0_START_ADDR_LO"), //            0x08
TEXT("REG_IO_MAP0_START_ADDR_HI"), //            0x09
TEXT("REG_IO_MAP0_END_ADDR_LO"), //              0x0A
TEXT("REG_IO_MAP0_END_ADDR_HI"), //              0x0B
TEXT("REG_IO_MAP1_START_ADDR_LO"), //            0x0C
TEXT("REG_IO_MAP1_START_ADDR_HI"), //            0x0D
TEXT("REG_IO_MAP1_END_ADDR_LO"), //              0x0E
TEXT("REG_IO_MAP1_END_ADDR_HI"), //              0x0F
TEXT("REG_MEM_MAP0_START_ADDR_LO"), //           0x10
TEXT("REG_MEM_MAP0_START_ADDR_HI"), //           0x11
TEXT("REG_MEM_MAP0_END_ADDR_LO"), //             0x12
TEXT("REG_MEM_MAP0_END_ADDR_HI"), //             0x13
TEXT("REG_MEM_MAP0_ADDR_OFFSET_LO"), //          0x14
TEXT("REG_MEM_MAP0_ADDR_OFFSET_HI"), //          0x15
TEXT("REG_GENERAL_CONTROL"), //                  0x16
NULL, //                                         0x17
TEXT("REG_MEM_MAP1_START_ADDR_LO"), //           0x18
TEXT("REG_MEM_MAP1_START_ADDR_HI"), //           0x19
TEXT("REG_MEM_MAP1_END_ADDR_LO"), //             0x1A
TEXT("REG_MEM_MAP1_END_ADDR_HI"), //             0x1B
TEXT("REG_MEM_MAP1_ADDR_OFFSET_LO"), //          0x1C
TEXT("REG_MEM_MAP1_ADDR_OFFSET_HI"), //          0x1D
TEXT("REG_GLOBAL_CONTROL"), //                   0x1E
NULL, //                                         0x1F
TEXT("REG_MEM_MAP2_START_ADDR_LO"), //           0x20
TEXT("REG_MEM_MAP2_START_ADDR_HI"), //           0x21
TEXT("REG_MEM_MAP2_END_ADDR_LO"), //             0x22
TEXT("REG_MEM_MAP2_END_ADDR_HI"), //             0x23
TEXT("REG_MEM_MAP2_ADDR_OFFSET_LO"), //          0x24
TEXT("REG_MEM_MAP2_ADDR_OFFSET_HI"), //          0x25
NULL, //                                         0x26
NULL, //                                         0x27
TEXT("REG_MEM_MAP3_START_ADDR_LO"), //           0x28
TEXT("REG_MEM_MAP3_START_ADDR_HI"), //           0x29
TEXT("REG_MEM_MAP3_END_ADDR_LO"), //             0x2A
TEXT("REG_MEM_MAP3_END_ADDR_HI"), //             0x2B
TEXT("REG_MEM_MAP3_ADDR_OFFSET_LO"), //          0x2C
TEXT("REG_MEM_MAP3_ADDR_OFFSET_HI"), //          0x2D
NULL, //                                         0x2E
NULL, //                                         0x2F
TEXT("REG_MEM_MAP4_START_ADDR_LO"), //           0x30
TEXT("REG_MEM_MAP4_START_ADDR_HI"), //           0x31
TEXT("REG_MEM_MAP4_END_ADDR_LO"), //             0x32
TEXT("REG_MEM_MAP4_END_ADDR_HI"), //             0x33
TEXT("REG_MEM_MAP4_ADDR_OFFSET_LO"), //          0x34
TEXT("REG_MEM_MAP4_ADDR_OFFSET_HI")  //          0x35
};


VOID
DisplaySocketRegister(
    UINT socket,
    UCHAR reg,
    UCHAR value
    )
{
    if (reg > (REG_LAST_INDEX+1)) return;

    if (RegisterNames[reg] != NULL) {
        DEBUGMSG(ZONE_PDD,
            (TEXT("PCMCIA:PCIC Register[%d:%2x:%s] = 0x%x\r\n"),
            socket, reg, RegisterNames[reg & 0x3f], value));
    }
}


VOID
DumpSocketRegisters(
    UINT socket
    )
{
    UCHAR i;

    for (i = 0; i < REG_LAST_INDEX+1; i++) {
        PCICIndex(socket, i);
        SocketRegisters[socket][i] = PCICDataRead();
        DisplaySocketRegister(socket, i, SocketRegisters[socket][i]);
    }
}

VOID
DeltaSocketRegisters(
    UINT socket
    )
{
    UCHAR CurrentRegisters[REG_LAST_INDEX];
    UCHAR i;

    for (i = 0; i < REG_LAST_INDEX+1; i++) {
        PCICIndex(socket, i);
        CurrentRegisters[i] = PCICDataRead();
    }

    for (i = 0; i < REG_LAST_INDEX+1; i++) {
        if (CurrentRegisters[i] != SocketRegisters[socket][i]) {
            DisplaySocketRegister(socket, i, CurrentRegisters[i]);
            SocketRegisters[socket][i] = CurrentRegisters[i];
        }
    }
}

#endif