socket.c

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C语言 代码 · 共 689 行 · 第 1/2 页

/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995-2000 Microsoft Corporation.  All rights reserved.

Module Name:  

   socket.c
   
Abstract:  

Notes: 
--*/

#include <windows.h>
#include <types.h>
#include <cardserv.h>
#include <sockserv.h>
#include <sockpd.h>
#include <memory.h>
// #include <pc.h>


//#define FORCE_POLLING 1

//
// CEPC PCMCIA Socket Services Socket APIs:
//    PDCardInquireSocket
//    PDCardGetSocket
//    PDCardSetSocket
//    PDCardInquireAdapter
//

#define NUM_SOCKETS 2
#define NUM_POWER_ENTRIES 4
#define VCC_DEFAULT_INDEX 2

//
// @doc DRIVERS
//

PDCARD_ADAPTER_INFO v_AdapterInfo = {
    1,  // memory granularity (for production platforms, this should be 1)
    0,  // adapter capabilities
    8,  // cache line size in 32-bit words
    NUM_POWER_ENTRIES
};

PDCARD_POWER_ENTRY v_PowerEntries[NUM_POWER_ENTRIES] = {
 { 0,    PWR_SUPPLY_VCC | PWR_SUPPLY_VPP1 | PWR_SUPPLY_VPP2 },
 { 33,   PWR_SUPPLY_VCC },
 { 50,   PWR_SUPPLY_VCC | PWR_SUPPLY_VPP1 | PWR_SUPPLY_VPP2 },
 { 120,  PWR_SUPPLY_VPP1 | PWR_SUPPLY_VPP2 }
};

PDCARD_SOCKET_STATE v_SockState[NUM_SOCKETS] = {
{
    SOCK_CAP_IO,
#ifdef FORCE_POLLING
    EVENT_MASK_BATTERY_DEAD|EVENT_MASK_BATTERY_LOW|
#else
    EVENT_MASK_BATTERY_DEAD|EVENT_MASK_BATTERY_LOW|EVENT_MASK_CARD_DETECT|
#endif
        EVENT_MASK_WRITE_PROTECT,   // status change interrupt mask
    0,  // present socket state
    0,  // control and indicators
    0,  // interface type
    0,  // Vcc
    0,  // Vpp1
    0   // Vpp2
},
{
    SOCK_CAP_IO,
#ifdef FORCE_POLLING
    EVENT_MASK_BATTERY_DEAD|EVENT_MASK_BATTERY_LOW|
#else
    EVENT_MASK_BATTERY_DEAD|EVENT_MASK_BATTERY_LOW|EVENT_MASK_CARD_DETECT|
#endif
        EVENT_MASK_WRITE_PROTECT,   // status change interrupt mask
    0,  // present socket state
    0,  // control and indicators
    0,  // interface type
    0,  // Vcc
    0,  // Vpp1
    0   // Vpp2
}
};

extern DWORD g_Irq; // PCMCIA IRQ set in init.c

//
// Set the socket controller registers to initial state with no card inserted.
//
VOID InitSocketNoCard(UINT32 uSocket, BOOL bUserMode)
{
    UCHAR tmp;
    UINT32 status; 
    UINT32 i; 
    UINT32 first, last;
    PDCARD_WINDOW_STATE WinState;

    PCICIndex(uSocket, REG_POWER_CONTROL);
    PCICDataWrite(PWR_AUTO_POWER);
    tmp = CFG_CARD_DETECT_ENABLE | (UCHAR)(g_Irq << 4);
    PCICIndex(uSocket, REG_STATUS_CHANGE_INT_CONFIG);
    PCICDataWrite(tmp);
    
    //
    // Disable the I/O windows
    //
    first = (uSocket == 0) ? SOCKET0_FIRST_IO_WINDOW : SOCKET1_FIRST_IO_WINDOW;
    last = first + 2;
    for (i = first; i < last; i++) {
        status = PDCardGetWindow(i, &WinState);
        if (status == CERR_SUCCESS) {
            WinState.fState &= ~WIN_STATE_ENABLED;
            WinState.uOffset = 0;
            // set the high bit in the window index if we are in kernel-mode
            PDCardSetWindow(bUserMode ? i : (i|ADP_STATE_KERNEL_MODE), &WinState);
        }
    }
}

//
// PDCardGetSocket
//
// @func    STATUS | PDCardGetSocket | Get the socket state of the specified socket.
// @rdesc   Returns one of the CERR_* return codes in cardserv.h.
//
// @comm    This function reads the specified socket's state and returns it in
//          the PDCARD_SOCKET_STATE structure.
//
STATUS
PDCardGetSocket(
    UINT32 uSocket,             // @parm Socket number (first socket is 0)
    PPDCARD_SOCKET_STATE pState // @parm Pointer to PDCARD_SOCKET_STATE structure
    )
{
    UINT8 tmp;
    PPDCARD_SOCKET_STATE pPDDState;

    if (uSocket >= NUM_SOCKETS) {
        return CERR_BAD_SOCKET;
    }

    pPDDState = &v_SockState[uSocket];
    
    EnterCriticalSection(&g_PCIC_Crit);

    pPDDState->fNotifyEvents = 0;        // Start off with nothing

    //
    // First acknowledge any status change interrupts
    //
    PCICIndex(uSocket, REG_CARD_STATUS_CHANGE);
    tmp = PCICDataRead();
/*
DEBUGMSG(ZONE_PDD,
    (TEXT("PDCardGetSocket(%d) REG_CARD_STATUS_CHANGE(0x%x) = 0x%x\r\n"),
    uSocket, REG_CARD_STATUS_CHANGE, tmp));
*/

    //
    // Figure out the socket state
    //
    PCICIndex(uSocket, REG_INTERFACE_STATUS);
    tmp = PCICDataRead();
/*
DEBUGMSG(ZONE_PDD,
    (TEXT("PDCardGetSocket(%d) REG_INTERFACE_STATUS(0x%x) = 0x%x\r\n"),
    uSocket, REG_INTERFACE_STATUS, tmp));
*/

    if ((tmp & (STS_CD1|STS_CD2)) == (STS_CD1|STS_CD2)) {
        pPDDState->fNotifyEvents |= EVENT_MASK_CARD_DETECT;
//DEBUGMSG(ZONE_PDD, (TEXT("PDCardGetSocket(%d) CARD_DETECT\r\n"), uSocket));
    } else {
//DEBUGMSG(ZONE_PDD, (TEXT("PDCardGetSocket(%d) ~CARD_DETECT\r\n"), uSocket));
        InitSocketNoCard(uSocket, FALSE);
        goto pcgs_exit;
    }

#ifdef NOT_IMPLEMENTED
    switch (tmp & (STS_BVD1|STS_BVD2)) {
    case STS_BVD1:
        pPDDState->fNotifyEvents |= EVENT_MASK_BATTERY_LOW;
DEBUGMSG(ZONE_PDD, (TEXT("PDCardGetSocket(%d) BATTERY_LOW\r\n"), uSocket));
        break;

    case STS_BVD2:
    case 0:
DEBUGMSG(ZONE_PDD, (TEXT("PDCardGetSocket(%d) BATTERY_DEAD\r\n"), uSocket));
        pPDDState->fNotifyEvents |= EVENT_MASK_BATTERY_DEAD;
        break;
    }
#endif NOT_IMPLEMENTED

    if (tmp & STS_WRITE_PROTECT) {
DEBUGMSG(ZONE_PDD, (TEXT("PDCardGetSocket(%d) WRITE_PROTECT\r\n"), uSocket));
        pPDDState->fNotifyEvents |= EVENT_MASK_WRITE_PROTECT;
    }


    if (tmp & STS_CARD_READY) {
//DEBUGMSG(ZONE_PDD, (TEXT("PDCardGetSocket(%d) CARD_READY\r\n"), uSocket));
        pPDDState->fNotifyEvents |= EVENT_MASK_CARD_READY;
    }

pcgs_exit:
    memcpy(pState, pPDDState, sizeof(PDCARD_SOCKET_STATE));
    LeaveCriticalSection(&g_PCIC_Crit);
    return CERR_SUCCESS;
}   // PDDCardGetSocket


//
// PDCardSetSocket
//
// @func    STATUS | PDCardSetSocket | Set the socket state of the specified socket.
// @rdesc   Returns one of the CERR_* return codes in cardserv.h.
//
// @comm    This function sets the specified socket's state and adjusts the socket
//          controller appropriately.
//          PDCardGetSocketState will usually be called first and adjustments will
//          be made to the PDCARD_SOCKET_STATE structure before PDCardSetSocketState
//          is called.  This avoids duplicated socket state on different layers and
//          it avoids unintentionally setting socket parameters.
//
// @xref <f PDCardGetSocketState>
//
STATUS
PDCardSetSocket(
    UINT32 uSocket,             // @parm Socket number (first socket is 0)
    PPDCARD_SOCKET_STATE pState // @parm Pointer to PDCARD_SOCKET_STATE structure
    )
{
    UINT8 tmp;
    PPDCARD_SOCKET_STATE pPDDState;
    STATUS ret;
    int t;
    UINT8 intctl;

    DEBUGMSG(ZONE_PDD, (TEXT("PDCardSetSocket(%d) entered\r\n"), uSocket));

    if (uSocket >= NUM_SOCKETS) {
        ret = CERR_BAD_SOCKET;
        goto pcss_fail;
    }

    //
    // Check socket power level indexes
    //
    if ((pState->fVcc & SOCK_VCC_LEVEL_MASK) >= NUM_POWER_ENTRIES ||
        !(v_PowerEntries[pState->fVcc & SOCK_VCC_LEVEL_MASK].fSupply & PWR_SUPPLY_VCC)) {
        ret = CERR_BAD_VCC;
        goto pcss_fail;
    }
    if (pState->uVpp1 >= NUM_POWER_ENTRIES || pState->uVpp2 >= NUM_POWER_ENTRIES ||
        !(v_PowerEntries[pState->uVpp1].fSupply & PWR_SUPPLY_VPP1) ||
        !(v_PowerEntries[pState->uVpp2].fSupply & PWR_SUPPLY_VPP2)) {
        ret = CERR_BAD_VPP;
        goto pcss_fail;
    }

    EnterCriticalSection(&g_PCIC_Crit);

    PCICIndex(uSocket, REG_INTERFACE_STATUS);
    tmp = PCICDataRead();

    if ((tmp & (STS_CD1|STS_CD2)) != (STS_CD1|STS_CD2)) {
        DEBUGMSG(ZONE_PDD,
            (TEXT("PDCardSetSocket(%d) No card inserted\r\n"), uSocket));
        InitSocketNoCard(uSocket, FALSE);
        goto pcss_exit;
    }

    pPDDState = &v_SockState[uSocket];

    //
    // Set the status change interrupt sources
    //
    tmp = (UCHAR)(g_Irq << 4); // CFG_MANAGEMENT_IRQ_BIT* bits will be set

    if (pState->fInterruptEvents & EVENT_MASK_CARD_DETECT) {
        tmp |= CFG_CARD_DETECT_ENABLE;
    }
    if (pState->fInterruptEvents & EVENT_MASK_BATTERY_DEAD) {
        tmp |= CFG_BATTERY_DEAD_ENABLE;
    }
    if (pState->fInterruptEvents & EVENT_MASK_BATTERY_LOW) {
        tmp |= CFG_BATTERY_WARNING_ENABLE;
    }
    if (pState->fIREQRouting & SOCK_IREQ_ENABLE) {
        tmp |= CFG_READY_ENABLE;
    } 
    PCICIndex(uSocket, REG_STATUS_CHANGE_INT_CONFIG);
    PCICDataWrite(tmp);
DEBUGMSG(ZONE_PDD,
    (TEXT("PDCardSetSocket(%d) REG_STATUS_CHANGE_INT_CONFIG(0x%x) = 0x%x\r\n"),
    uSocket, REG_STATUS_CHANGE_INT_CONFIG, tmp));

    //
    // Enable or disable IREQ interrupts
    //
    PCICIndex(uSocket, REG_INTERRUPT_AND_GENERAL_CONTROL);
    tmp = PCICDataRead();
    tmp &= (UCHAR)~g_Irq; // Turn off INT_IRQ_BIT* bits
    if (pState->fIREQRouting & SOCK_IREQ_ENABLE) {
        tmp |= ((UCHAR)g_Irq)|INT_CARD_NOT_RESET; // Turn on INT_IRQ_BIT* bits
    } else {
        tmp |= INT_CARD_NOT_RESET;
    }
    PCICDataWrite(tmp);

DEBUGMSG(1,
    (TEXT("PDCardSetSocket voltage = %d\r\n"),
     v_PowerEntries[pState->fVcc & SOCK_VCC_LEVEL_MASK].uPowerLevel));
    // ignore Vpp 
    if ((pState->fVcc & SOCK_VCC_LEVEL_MASK) != (pPDDState->fVcc & SOCK_VCC_LEVEL_MASK)) {
        //
        // Set socket power as requested.
        //
        switch (v_PowerEntries[pState->fVcc & SOCK_VCC_LEVEL_MASK].uPowerLevel) {
        case 0:
            PCICIndex(uSocket, REG_POWER_CONTROL);
            PCICDataWrite(0);
            goto pcss_exit; // this is what it used to do so I won't change it
        case 33:
            PCICIndex(uSocket, 0x16);//REG_MISC_CONTROL_1);
            PCICDataWrite(0x02);  // enable 3.3V
            break;
        case 50:
            PCICIndex(uSocket, 0x16);//REG_MISC_CONTROL_1);
            if (PCICDataRead() & 0x01) // i.e., if we detect a 5V card:
                PCICDataWrite(0x00);  // disable 3.3V (i.e., use 5V)
            else
                // this is a 3.3V ONLY card and mustn't be powered at 5V
                // so ignore the command; we'd assert here save that card
                // services will attempt to apply 5V to read the CIS.
                PCICDataWrite(0x02);  // enable 3.3V
            break;
        default:
            ASSERT(0); // this ought to have been caught above