sa_lcd2.cpp
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C++ 代码 · 共 824 行 · 第 1/2 页
CPP
824 行
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995-2000 Microsoft Corporation. All rights reserved.
Module Name:
Abstract:
Functions:
Notes:
--*/
#include "precomp.h"
#include "Palette.h" /* bring in const palette definition for 256 color palette */
#if 1
#undef DEBUGMSG
#define DEBUGMSG(cond,msg) RETAILMSG(cond,msg)
#define GPE_ZONE_INIT 1
#define GPE_ZONE_ERROR 2
#define GPE_ZONE_CURSOR 3
#endif
// Physical address used to create the virtual address for access to the LCD control registers
#define LCD_BASE_VIRTUAL 0xAB100000 /*was 0xAB100000*/ /* LCCR0: 0xB0100000 */
// Physical address used to create the virtual address for our frame and palette buffer
#define GPIO_BASE_VIRTUAL 0xA9040000 /*was 0xA9040000*/ /* GPLR: 0x90040000 */
// Physical address for base of palette (and frame buffer)
// This physical address is loaded into SA1110 (DBAR1:0xB0100010) for base of video frame buffer
#define FRAME_AND_PALETTE_PHYSICAL 0xC1D00000
// Physical address used to create the virtual address for our frame and palette buffer
#define LCD_VIRTUAL_FRAME_BASE 0xADD00000
//-------------------------------------------
// Defines for 640x480x8bpp STN display...
#define DOTS_WIDE 640
#define DOTS_TALL 480
#define COLOR_DEPTH 8
#define PALETTE_ENTRIES 256
#define PALETTE_SIZE_BYTES (PALETTE_ENTRIES*2) /* 256 entries, each 2 bytes large */
#define FRAME_AND_PALETTE_SIZE (DOTS_WIDE*DOTS_TALL + PALETTE_SIZE_BYTES)
//-------------------------------------------
INSTANTIATE_GPE_ZONES(0x3,"MGDI Driver","unused1","unused2") // Start with errors and warnings
static GPE *gGPE = (GPE*)NULL;
static ulong gBitMasks[] = { 0xF800, 0x07E0, 0x001F }; // 565 MODE
// This prototype avoids problems exporting from .lib
BOOL APIENTRY GPEEnableDriver(ULONG engineVersion, ULONG cj, DRVENABLEDATA *data,
PENGCALLBACKS engineCallbacks);
BOOL APIENTRY DrvEnableDriver(ULONG engineVersion, ULONG cj, DRVENABLEDATA *data,
PENGCALLBACKS engineCallbacks)
{
return GPEEnableDriver(engineVersion, cj, data, engineCallbacks);
}
//
// Main entry point for a GPE-compliant driver
//
GPE *GetGPE(void)
{
if (!gGPE)
{
gGPE = new SA_LCD2();
}
return gGPE;
}
SA_LCD2::SA_LCD2 (void)
{
//DEBUGMSG(GPE_ZONE_INIT,(TEXT("SA_LCD2::SA_LCD2\r\n")));
// setup up display mode related constants
m_nScreenWidth = DOTS_WIDE;
m_nScreenHeight = DOTS_TALL;
m_colorDepth = COLOR_DEPTH;
m_cbScanLineLength = m_nScreenWidth;
m_FrameBufferSize = m_nScreenHeight * m_cbScanLineLength;
// setup ModeInfo structure
m_ModeInfo.modeId = 0;
m_ModeInfo.width = m_nScreenWidth;
m_ModeInfo.height = m_nScreenHeight;
m_ModeInfo.Bpp = m_colorDepth;
m_ModeInfo.format = gpe8Bpp;
m_ModeInfo.frequency = 60; // ?
m_pMode = &m_ModeInfo;
// memory map register access window, frame buffer, and program LCD controller
InitializeHardware();
// allocate primary display surface
m_pPrimarySurface = new GPESurf(m_nScreenWidth, m_nScreenHeight, (void*)(m_VirtualFrameBuffer + PALETTE_SIZE_BYTES), m_cbScanLineLength, m_ModeInfo.format);
memset ((void*)m_pPrimarySurface->Buffer(), 0x0, m_FrameBufferSize);
// init cursor related vars
m_CursorVisible = FALSE;
m_CursorDisabled = TRUE;
m_CursorForcedOff = FALSE;
memset (&m_CursorRect, 0x0, sizeof(m_CursorRect));
m_CursorBackingStore = NULL;
m_CursorXorShape = NULL;
m_CursorAndShape = NULL;
}
void SA_LCD2::InitializeHardware (void)
{
unsigned char *ptr;
unsigned short * palette;
//DEBUGMSG(1,(L"SA_LCD2::InitializeHardware()\r\n"));
// map LCD register access window into process space memory
// m_LCDRegs = (struct lcdregs *)VirtualAlloc (0, 0x1000, MEM_RESERVE, PAGE_NOACCESS);
// VirtualCopy ((void*)m_LCDRegs, (void*)LCD_BASE_VIRTUAL, 0x1000, PAGE_READWRITE | PAGE_NOCACHE);
m_LCDRegs = (struct lcdregs *)VirtualAllocCopy(0x1000, NULL, (PVOID)(LCD_BASE_VIRTUAL));
// map GPIO register access window into process space memory
// m_GPIORegs = (struct gpioreg *)VirtualAlloc (0, 0x1000, MEM_RESERVE, PAGE_NOACCESS);
// VirtualCopy ((void*)m_GPIORegs, (void*)GPIO_BASE_VIRTUAL, 0x1000, PAGE_READWRITE | PAGE_NOCACHE);
m_GPIORegs = (struct gpioreg *)VirtualAllocCopy(0x1000, NULL, (PVOID)(GPIO_BASE_VIRTUAL));
// map frame buffer into process space memory
// m_VirtualFrameBuffer = (DWORD)VirtualAlloc(0, 0x48000, MEM_RESERVE, PAGE_NOACCESS);
// VirtualCopy((void*)m_VirtualFrameBuffer, (void *)LCD_VIRTUAL_FRAME_BASE, 0x48000, PAGE_READWRITE | PAGE_NOCACHE);
m_VirtualFrameBuffer = (DWORD)VirtualAllocCopy(FRAME_AND_PALETTE_SIZE, NULL, (PVOID)(LCD_VIRTUAL_FRAME_BASE));
//RETAILMSG(1, (L"m_LCDRegs = %8.8x\nm_GPIORegs = %8.8x\nm_VirtualFrameBuffer = %8.8x\n", m_LCDRegs, m_GPIORegs, m_VirtualFrameBuffer));
// Load the palette for 8bpp usage.
// Each palette entry is 16 bits large (unsigned short).
// The first palette entry contains two bits of information needed by the display controler.
// Bits 13:12 contain the Pixel Bit Size (PBS)
// 00: 4 bits / pixel, 16-entry palette (32 bytes of palette buffer)
// 01: 8 bits / pixel, 256-entry palette (512 bytes of palette buffer)
// 10: 10-12 bits / pixel - passive mode (PAS=0), 16 bits / pixel - active mode (PAS=1)
// 11: reserved
// NOTE: for condition "10", the palette is unused, however, it is required to have 32 bytes of
// "dummy palette". Palette data mys be zero filled (except for these two bits in the first
// palette entry.)
//DEBUGMSG(1,(L"Initializing Palette\r\n"));
//void DispDrvrSetPalette (const PALETTEENTRY source[],unsigned short firstEntry,unsigned short numEntries)
{
int i;
int firstEntry=0;
int numEntries=PALETTE_ENTRIES;
int end = firstEntry + numEntries;
palette = (unsigned short *)m_VirtualFrameBuffer; // 1 ushort / palette entry (512 bytes)
PALETTEENTRY * source = (PALETTEENTRY *)_rgbIdentity;
for(i=firstEntry;i<end;i++) {
// Each palette entry is 12 bits - 11:8 Red, 7:4 Green, 3:0 Blue
palette[i] = (
((source[i].peBlue & 0xF0) >> 4) |
((source[i].peGreen & 0xF0) ) |
((source[i].peRed & 0xF0) << 4)
);
} // for
// Modify the PBS bits for 8 bpp operation...
palette[0] = ((palette[0] & (unsigned short)0x0FFF) | (unsigned short) 0x1000);
//DEBUGMSG(1,((L"Palette initialization complete %x\r\n"),palette[0]));
//for(i = 0; i<256; i++) {
// DEBUGMSG(1,((L"%04X\r\n"),palette[i]));
//}
}
//DEBUGMSG(1,(L"Load GPIO registers for LCD controller\r\n"));
// Program GPIO register to enable GPIO lines 2 - 9 for use by the LCD controller
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gpdr,gp02,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gpdr,gp03,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gpdr,gp04,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gpdr,gp05,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gpdr,gp06,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gpdr,gp07,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gpdr,gp08,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gpdr,gp09,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gafr,gp02,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gafr,gp03,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gafr,gp04,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gafr,gp05,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gafr,gp06,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gafr,gp07,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gafr,gp08,1);
WRITE_BITFIELD(struct gpioregBits,&m_GPIORegs->gafr,gp09,1);
//DEBUGMSG(1,(L"Load LCD controller registers\r\n"));
// b9 2f107a70 1f0c05df 70ff02
// disable LCD controller
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,len,0); // LCD Enable (LEN) - Disable LCD Controler
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,cms,0); // Color/Monochrome Select (CMS) color=0
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,sds,0); // Single/Dual Panel Select (SDS) single=0
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,bam,1); // Base Address Update Interrupt Mask (BAM) mask interrupt=1
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,ldm,1); // LCD Disable Done Interrupt Mask (LDM) mask interrupt=1
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,erm,1); // Error Interrupt Mask (ERM) mask error interrups=1
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,pas,1); // Passive/Active Select (PAS) passive STN=0
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,ble,0); // Big/Little Endian Select (BLE) little=0
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,dpd,0); // Double-Pixel Data Pin Mode (PDP) output 4 pixels on LDD3:0 lines=0
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,pdd,0); // Palette DMA Request Delay (PDD) <dma delay count>
m_LCDRegs->dbar1 = (DWORD)FRAME_AND_PALETTE_PHYSICAL;
WRITE_BITFIELD(struct lccr2Bits,&m_LCDRegs->lccr2,efw,12); // End-of-Frame Line Clock Wait Count (EFW)
WRITE_BITFIELD(struct lccr3Bits,&m_LCDRegs->lccr3,acb,((512-2)/2)); // AC Bias Pin Frequency (ACB)
WRITE_BITFIELD(struct lccr3Bits,&m_LCDRegs->lccr3,api,0); // AC Bias Pin Transitions Per Interrupt (API)
WRITE_BITFIELD(struct lccr3Bits,&m_LCDRegs->lccr3,vsp,1); // Vertial Sync Polarity (VSP)
WRITE_BITFIELD(struct lccr3Bits,&m_LCDRegs->lccr3,hsp,1); // Horizontal Sync Polarity (HSP)
WRITE_BITFIELD(struct lccr3Bits,&m_LCDRegs->lccr3,pcp,1); // Pixel Clock Polarity (PCP) rising edge=0
WRITE_BITFIELD(struct lccr3Bits,&m_LCDRegs->lccr3,oep,0); // Output Enable Polarity (OEP)
WRITE_BITFIELD(struct lccr2Bits,&m_LCDRegs->lccr2,vsw,(2-1)); // Vertical Sync Pulse Width (VSW)
WRITE_BITFIELD(struct lccr1Bits,&m_LCDRegs->lccr1,hsw,(96-2)); // Horzontal Sync Pulse Width (HSW)
WRITE_BITFIELD(struct lccr1Bits,&m_LCDRegs->lccr1,elw,(16)); // End-of-Line Pixel Clock Wait COunt (ELW)
WRITE_BITFIELD(struct lccr1Bits,&m_LCDRegs->lccr1,blw,(48-1)); // Beginning-of-Line Pixel Clock Wait Count (BLW)
WRITE_BITFIELD(struct lccr1Bits,&m_LCDRegs->lccr1,ppl,(640-16)); // Pixels Per Line (PPL) (dots wide - 16)
WRITE_BITFIELD(struct lccr2Bits,&m_LCDRegs->lccr2,lpp,(480-1)); // Lines Per Panel (LPP) (dots tall -1)
WRITE_BITFIELD(struct lccr2Bits,&m_LCDRegs->lccr2,bfw,31); // Beginning-of-Frame Clock Wait Count (BFW)
WRITE_BITFIELD(struct lccr3Bits,&m_LCDRegs->lccr3,pcd,((9-4)/2)); // Pixel Clock Divider (PCD)
//DEBUGMSG(1,(L"Clearing LCD controller status registers\r\n"));
// clear LCD Status Register
WRITE_BITFIELD(struct lcsrBits,&m_LCDRegs->lcsr,ber,1);
WRITE_BITFIELD(struct lcsrBits,&m_LCDRegs->lcsr,abc,1);
WRITE_BITFIELD(struct lcsrBits,&m_LCDRegs->lcsr,iol,1);
WRITE_BITFIELD(struct lcsrBits,&m_LCDRegs->lcsr,iul,1);
WRITE_BITFIELD(struct lcsrBits,&m_LCDRegs->lcsr,iou,1);
WRITE_BITFIELD(struct lcsrBits,&m_LCDRegs->lcsr,iuu,1);
WRITE_BITFIELD(struct lcsrBits,&m_LCDRegs->lcsr,ool,1);
WRITE_BITFIELD(struct lcsrBits,&m_LCDRegs->lcsr,oul,1);
WRITE_BITFIELD(struct lcsrBits,&m_LCDRegs->lcsr,oou,1);
WRITE_BITFIELD(struct lcsrBits,&m_LCDRegs->lcsr,ouu,1);
// enable LCD controller
WRITE_BITFIELD(struct lccr0Bits,&m_LCDRegs->lccr0,len,1); // LCD Enable (LEN) - Enable LCD Controler
//DEBUGMSG(1,((L"Regs %x %x %x %x\r\n"),m_LCDRegs->lccr0,m_LCDRegs->lccr1,m_LCDRegs->lccr2,m_LCDRegs->lccr3));
ptr=(unsigned char *)(&palette[256]);
//memset ((void*)ptr, 0, 640*480);
// for(int j=0; j<320; j++) {
// ptr[j]=1;
// }
}
SCODE SA_LCD2::SetMode (INT modeId, HPALETTE *palette)
{
//DEBUGMSG(GPE_ZONE_INIT,(TEXT("SA_LCD2::SetMode\r\n")));
if (modeId != 0)
{
DEBUGMSG(GPE_ZONE_ERROR,(TEXT("SA_LCD2::SetMode Want mode %d, only have mode 0\r\n"),modeId));
return E_INVALIDARG;
}
if (palette)
{
switch (m_colorDepth)
{
case 8:
*palette = EngCreatePalette (PAL_INDEXED,
PALETTE_SIZE,
(ULONG*)_rgbIdentity,
0,
0,
0);
break;
case 16:
case 24:
case 32:
break;
}
}
return S_OK;
}
SCODE SA_LCD2::GetModeInfo(GPEMode *mode, INT modeNumber)
{
//DEBUGMSG (GPE_ZONE_INIT, (TEXT("SA_LCD2::GetModeInfo\r\n")));
if (modeNumber != 0)
{
return E_INVALIDARG;
}
*mode = m_ModeInfo;
return S_OK;
}
int SA_LCD2::NumModes()
{
//DEBUGMSG (GPE_ZONE_INIT, (TEXT("SA_LCD2::NumModes\r\n")));
return 1;
}
void SA_LCD2::CursorOn (void)
{
UCHAR *ptrScreen = (UCHAR*)m_pPrimarySurface->Buffer();
UCHAR *ptrLine;
UCHAR *cbsLine;
UCHAR *xorLine;
UCHAR *andLine;
int x, y;
//DEBUGMSG(1,(L"SA_LCD2::CursorOn()\r\n"));
if (!m_CursorForcedOff && !m_CursorDisabled && !m_CursorVisible)
{
if (!m_CursorBackingStore)
{
DEBUGMSG (GPE_ZONE_ERROR, (TEXT("SA_LCD2::CursorOn - No backing store available\r\n")));
return;
}
for (y = m_CursorRect.top; y < m_CursorRect.bottom; y++)
{
if (y < 0)
{
continue;
}
if (y >= m_nScreenHeight)
{
break;
}
ptrLine = &ptrScreen[y * m_pPrimarySurface->Stride()];
cbsLine = &m_CursorBackingStore[(y - m_CursorRect.top) * (m_CursorSize.x * (m_colorDepth >> 3))];
xorLine = &m_CursorXorShape[(y - m_CursorRect.top) * m_CursorSize.x];
andLine = &m_CursorAndShape[(y - m_CursorRect.top) * m_CursorSize.x];
for (x = m_CursorRect.left; x < m_CursorRect.right; x++)
{
if (x < 0)
{
continue;
}
if (x >= m_nScreenWidth)
{
break;
}
cbsLine[(x - m_CursorRect.left) * (m_colorDepth >> 3)] = ptrLine[x * (m_colorDepth >> 3)];
ptrLine[x * (m_colorDepth >> 3)] &= andLine[x - m_CursorRect.left];
ptrLine[x * (m_colorDepth >> 3)] ^= xorLine[x - m_CursorRect.left];
if (m_colorDepth > 8)
{
cbsLine[(x - m_CursorRect.left) * (m_colorDepth >> 3) + 1] = ptrLine[x * (m_colorDepth >> 3) + 1];
ptrLine[x * (m_colorDepth >> 3) + 1] &= andLine[x - m_CursorRect.left];
ptrLine[x * (m_colorDepth >> 3) + 1] ^= xorLine[x - m_CursorRect.left];
if (m_colorDepth > 16)
{
cbsLine[(x - m_CursorRect.left) * (m_colorDepth >> 3) + 2] = ptrLine[x * (m_colorDepth >> 3) + 2];
ptrLine[x * (m_colorDepth >> 3) + 2] &= andLine[x - m_CursorRect.left];
ptrLine[x * (m_colorDepth >> 3) + 2] ^= xorLine[x - m_CursorRect.left];
}
}
}
}
m_CursorVisible = TRUE;
}
}
void SA_LCD2::CursorOff (void)
{
UCHAR *ptrScreen = (UCHAR*)m_pPrimarySurface->Buffer();
UCHAR *ptrLine;
UCHAR *cbsLine;
int x, y;
//DEBUGMSG(1,(L"SA_LCD2::CursorOff()\r\n"));
if (!m_CursorForcedOff && !m_CursorDisabled && m_CursorVisible)
{
if (!m_CursorBackingStore)
{
DEBUGMSG (GPE_ZONE_ERROR, (TEXT("SA_LCD2::CursorOff - No backing store available\r\n")));
return;
}
for (y = m_CursorRect.top; y < m_CursorRect.bottom; y++)
{
// clip to displayable screen area (top/bottom)
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