cshrd.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 775 行 · 第 1/3 页
H
775 行
/****************************************************************************
(C) Unpublished Work of ZeitNet, Inc. All Rights Reserved. *
*
THIS WORK IS AN UNPUBLISHED WORK AND CONTAINS CONFIDENTIAL, *
PROPRIETARY AND TRADE SECRET INFORMATION OF ZEITNET, INC. ACCESS *
TO THIS WORK IS RESTRICTED TO (I) ZEITNET EMPLOYEES WHO HAVE A *
NEED TO KNOW TO PERFORM TASKS WITHIN THE SCOPE OF THEIR ASSIGNMENTS *
AND (II) ENTITIES OTHER THAN ZEITNET WHO HAVE ENTERED INTO *
APPROPRIATE LICENSE AGREEMENTS. NO PART OF THIS WORK MAY BE USED, *
PRACTICED, PERFORMED, COPIED, DISTRIBUTED, REVISED, MODIFIED, *
TRANSLATED, ABRIDGED, CONDENSED, EXPANDED, COLLECTED, COMPILED, *
LINKED,RECAST, TRANSFORMED, ADAPTED IN ANY FORM OR BY ANY MEANS, *
MANUAL, MECHANICAL, CHEMICAL, ELECTRICAL, ELECTRONIC, OPTICAL, *
BIOLOGICAL, OR OTHERWISE WITHOUT THE PRIOR WRITTEN PERMISSION AND *
CONSENT OF ZEITNET. ANY USE OR EXPLOITATION OF THIS WORK WITHOUT *
THE PRIOR WRITTEN CONSENT OF ZEITNET COULD SUBJECT THE PERPETRATOR *
TO CRIMINAL AND CIVIL LIABILITY. *
*
****************************************************************************/
//---------------------------------------------------------------------------
//
// Copyright (C) 1996-1997. Unpublished Work of Crystal Semiconductor Corp.
// All Rights Reserved.
//
// THIS WORK IS AN UNPUBLISHED WORK AND CONTAINS CONFIDENTIAL,
// PROPRIETARY AND TRADE SECRET INFORMATION OF CRYSTAL SEMICONDUCTOR.
// ACCESS TO THIS WORK IS RESTRICTED TO (I) CRYSTAL SEMICONDUCTOR EMPLOYEES
// WHO HAVE A NEED TO KNOW TO PERFORM TASKS WITHIN THE SCOPE OF THEIR
// ASSIGNMENTS AND (II) ENTITIES OTHER THAN CRYSTAL SEMICONDUCTOR WHO
// HAVE ENTERED INTO APPROPRIATE LICENSE AGREEMENTS. NO PART OF THIS
// WORK MAY BE USED, PRACTICED, PERFORMED, COPIED, DISTRIBUTED, REVISED,
// MODIFIED, TRANSLATED, ABRIDGED, CONDENSED, EXPANDED, COLLECTED,
// COMPILED,LINKED,RECAST, TRANSFORMED, ADAPTED IN ANY FORM OR BY ANY
// MEANS,MANUAL, MECHANICAL, CHEMICAL, ELECTRICAL, ELECTRONIC, OPTICAL,
// BIOLOGICAL, OR OTHERWISE WITHOUT THE PRIOR WRITTEN PERMISSION AND
// CONSENT OF CRYSTAL SEMICONDUCTOR . ANY USE OR EXPLOITATION OF THIS WORK
// WITHOUT THE PRIOR WRITTEN CONSENT OF CRYSTAL SEMICONDUCTOR COULD
// SUBJECT THE PERPETRATOR TO CRIMINAL AND CIVIL LIABILITY.
//
//---------------------------------------------------------------------------
/*++
Copyright (c) 1994 ZeitNet Inc.
Module Name:
cshrd.h
Abstract:
This file contains the hardware-related definitions for
the CRYSTAL driver.
Author:
Sateesh. A Kumar(Sat).
Creation date 11-Mar-1994
Environment:
This driver is expected to work in DOS, OS2 and NT at the equivalent
of kernel mode.
Architecturally, there is an assumption in this driver that we are
on a little endian machine.
Revision History:
12 November 1994 10:00 ASK/PI
- Modified PACKET_PAGE structures to reflect changes incorporated
in data sheet of CS8921 v0.21 October 6 1994.
- Structure for PnP (Plug and Play) registers were defined.
- A new bit CRYSTAL_LCR_NWAY_ENABLE is introduced in Line control Register.
- A new bit CRYSTAL_LCR_NWAY_PULSES is introduced in Line control Register.
- A new bit CRYSTAL_LSR_NWAY_FDX is introduced in Line Status Register.
- A new bit CRYSTAL_LSR_NWAY_ACTIVE is introduced in Line Status Register.
By Date
Prashanth (PI) 5-1-95
Struture for CRYSTAL_DMA_FRAME is defined
By : Prashanth
DATE : 19 th May 1995
VERSION : 0.02
This code is merged for sparrow and rattler. The Code can auto
Detect type of card and configure accordingly
DATE : 25 th May 1995
- This header file has defines for EEPROM Ver .01
DATE : 14 th Jun 1995
VERSION : 1.0
-----------------------------------------------------------------------------
DATE : 10th May 1996
VERSION : 2.29
PERSON : Mike Gibson
Change Flag: @250
Add definition for EEPROM bit that indicates the driver should load
even if the cable is not attached.
-----------------------------------------------------------------------------
DATE : 07th Nov 1996
VERSION : 2.30
PERSON : Bob Sharp
Change Flag: @253
Added support for detecting Chip Revision
-----------------------------------------------------------------------------
--*/
#ifndef _CRYSTALHARDWARE_
#define _CRYSTALHARDWARE_
//#define CS8921 0
#define CS89XX_ID 0x630e
#define CS8900_PROD_ID_LOW 0x0
#define CS8920_PROD_ID_LOW 0x4000
//@105 add mongoose support
#define CS89xx_PROD_ID_LOW 0x6000 //@105
#define PRODUCT_ID_MASK 0xE000
#define REVISION_ID_MASK 0x1f00 //@253
//
// Include processor-specific definitions needed by the CS8921.
// Macros for CRYSTAL_READ_PORT, CRYSTAL_WRITE_PORT etc.
//#include <csdet.h>
#define CRYSTAL_CHIPEISA_ID ((USHORT)(0x0000)) // offset 0-> Corp -ID
#define CRYSTAL_PRODUCT_ID ((USHORT)(0x0002)) // offset 02h
#define CRYSTAL_ISA_IO_BASE_ADDRESS ((USHORT)(0x0020)) // offset 20h
#define CRYSTAL_ISA_INTERRUPT_NUMBER ((USHORT)(0x0022)) // offset 22h
#define CRYSTAL_ISA_DMA_CHANNEL ((USHORT)(0x0024)) // offset 24h
#define CRYSTAL_ISA_DMA_START_OF_FRAME_OFFSET ((USHORT)(0x0026)) // offset 26h
#define CRYSTAL_ISA_DMA_FRAME_COUNT ((USHORT)(0x0028)) // offset 28h
#define CRYSTAL_ISA_DMA_BYTE_COUNT ((USHORT)(0x002A)) // offset 2Ah
#define CRYSTAL_ISA_MEMORY_BASE_ADDRESS ((USHORT)(0x002C)) // offset 2Ch
#define CRYSTAL_BOOT_PROM_BASE_ADDRESS ((USHORT)(0x0030)) // offset 30h
#define CRYSTAL_BOOT_PROM_ADDRESS_MASK ((USHORT)(0x0034)) // offset 34h
#define CRYSTAL_EEPROM_COMMAND_REGISTER ((USHORT)(0x0040)) // offset 40h
#define CRYSTAL_EEPROM_DATA_WORD ((USHORT)(0x0042)) // offset 42h
#define CRYSTAL_FRAME_BYTE_COUNT ((USHORT)(0x0050)) // offset 50h // @258a
#define CRYSTAL_RX_CONFIG_REGISTER ((USHORT)(0x0102)) // offset 102h
#define CRYSTAL_RX_CONTROL_REGISTER ((USHORT)(0x0104)) // offset 104h
#define CRYSTAL_TX_CONFIG_REGISTER ((USHORT)(0x0106)) // offset 106h
#define CRYSTAL_TX_COMMAND_REGISTER ((USHORT)(0x0108)) // offset 108h
#define CRYSTAL_BUFFER_CONFIG_REGISTER ((USHORT)(0x010A)) // offset 10Ah
#define CRYSTAL_LINE_CONTROL_REGISTER ((USHORT)(0x0112)) // offset 112h
#define CRYSTAL_SELF_CONTROL_REGISTER ((USHORT)(0x0114)) // offset 114h
#define CRYSTAL_BUS_CONTROL_REGISTER ((USHORT)(0x0116)) // offset 116h
#define CRYSTAL_TEST_CONTROL_REGISTER ((USHORT)(0x0118)) // offset 118h
#define CRYSTAL_AUTO_NEG_CONTROL_REGISTER ((USHORT)(0x011C)) // offset 11Ch
#define CRYSTAL_INTERRUPT_STATUS_QUEUE ((USHORT)(0x0120)) // offset 120h
#define CRYSTAL_RX_EVENT_REGISTER ((USHORT)(0x0124)) // offset 124h
#define CRYSTAL_TX_EVENT_REGISTER ((USHORT)(0x0128)) // offset 128h
#define CRYSTAL_BUF_EVENT_REGISTER ((USHORT)(0x012C)) // offset 12Ch
#define CRYSTAL_RX_MISS_COUNT ((USHORT)(0x0130)) // offset 130h
#define CRYSTAL_TX_COL_COUNT ((USHORT)(0x0132)) // offset 132h
#define CRYSTAL_LINE_STATUS_REGISTER ((USHORT)(0x0134)) // offset 134h
#define CRYSTAL_SELF_STATUS_REGISTER ((USHORT)(0x0136)) // offset 136h
#define CRYSTAL_BUS_STATUS_REGISTER ((USHORT)(0x0138)) // offset 138h
#define CRYSTAL_TDR_REGISTER ((USHORT)(0x013C)) // offset 13Ch
#define CRYSTAL_AUTO_NEG_STATUS_REGISTER ((USHORT)(0x013E)) // offset 13Eh
#define CRYSTAL_TX_COMMAND ((USHORT)(0x0144)) // offset 144h
#define CRYSTAL_TX_LENGTH ((USHORT)(0x0146)) // offset 146h
#define CRYSTAL_LOGICAL_ADDRESS_FILTER ((USHORT)(0x0150)) // offset 150h
#define CRYSTAL_INDIVIDUAL_ADDRESS ((USHORT)(0x0158)) // offset 158h
#define CRYSTAL_RECEIVE_STATUS ((USHORT)(0x0400)) // offset 400h
#define CRYSTAL_RECEIVE_LENGTH ((USHORT)(0x0402)) // offset 402h
#define CRYSTAL_RECEIVE_FRAME_PTR ((USHORT)(0x0404)) // offset 404h
#define CRYSTAL_TRANSMIT_FRAME_PTR ((USHORT)(0x0A00)) // offset A00h
//
// Following are the PacketPage Offsets to Plug and Play registers.
//
#define CRYSTAL_PNP_REG_ACTIVATE ((USHORT)(0x0330)) // Packet Page 0x330.
#define CRYSTAL_PNP_REG_IO_RANGE_CHECK ((USHORT)(0x0331)) // Packet Page 0x331.
#define CRYSTAL_PNP_REG_MBAH0 ((USHORT)(0x0340)) // Packet Page 0x340.
#define CRYSTAL_PNP_REG_MBAL0 ((USHORT)(0x0341)) // Packet Page 0x341.
#define CRYSTAL_PNP_REG_MCNTL0 ((USHORT)(0x0342)) // Packet Page 0x342.
#define CRYSTAL_PNP_REG_MRLH0 ((USHORT)(0x0343)) // Packet Page 0x343.
#define CRYSTAL_PNP_REG_MRLL0 ((USHORT)(0x0344)) // Packet Page 0x344.
#define CRYSTAL_PNP_REG_MBAH1 ((USHORT)(0x0348)) // Packet Page 0x348.
#define CRYSTAL_PNP_REG_MBAL1 ((USHORT)(0x0349)) // Packet Page 0x349.
#define CRYSTAL_PNP_REG_MCNTL1 ((USHORT)(0x034a)) // Packet Page 0x34a.
#define CRYSTAL_PNP_REG_IO_BAH0 ((USHORT)(0x0360)) // Packet Page 0x360.
#define CRYSTAL_PNP_REG_IO_BAL0 ((USHORT)(0x0361)) // Packet Page 0x361.
#define CRYSTAL_PNP_REG_IRQ_S0 ((USHORT)(0x0370)) // Packet Page 0x370.
#define CRYSTAL_PNP_REG_IRQ_TS0 ((USHORT)(0x0371)) // Packet Page 0x371.
#define CRYSTAL_PNP_REG_DMASX ((USHORT)(0x0374)) // Packet Page 0x374.
#define CRYSTAL_PNP_TEST_REGISTER ((USHORT)(0x03F0)) // Packet Page 0x3F0.
#define CRYSTAL_PNP_REG_IO_DEF_VAL1 ((USHORT)(0x03F1)) // Packet Page 0x3F1.
//
// End of Packet Page Offset Equates
//
//
// Following are the address of Plug and Play registers.
//
#define PNP_REG_ACTIVATE ((USHORT)(0x030)) // Plug and play 0x30.
#define PNP_REG_IO_RANGE_CHECK ((USHORT)(0x031)) // Plug and play 0x31.
#define PNP_REG_MBAH0 ((USHORT)(0x040)) // Plug and play 0x40.
#define PNP_REG_MBAL0 ((USHORT)(0x041)) // Plug and play 0x41.
#define PNP_REG_MCNTL0 ((USHORT)(0x042)) // Plug and play 0x42.
#define PNP_REG_MRLH0 ((USHORT)(0x043)) // Plug and play 0x43.
#define PNP_REG_MRLL0 ((USHORT)(0x044)) // Plug and play 0x44.
#define PNP_REG_MBAH1 ((USHORT)(0x048)) // Plug and play 0x48.
#define PNP_REG_MBAL1 ((USHORT)(0x049)) // Plug and play 0x49.
#define PNP_REG_MCNTL1 ((USHORT)(0x04a)) // Plug and play 0x4a.
#define PNP_REG_IO_BAH0 ((USHORT)(0x060)) // Plug and play 0x60.
#define PNP_REG_IO_BAL0 ((USHORT)(0x061)) // Plug and play 0x61.
#define PNP_REG_IRQ_S0 ((USHORT)(0x070)) // Plug and play 0x70.
#define PNP_REG_IRQ_TS0 ((USHORT)(0x071)) // Plug and play 0x71.
#define PNP_REG_DMASX ((USHORT)(0x074)) // Plug and play 0x74.
#define PNP_TEST_REGISTER ((USHORT)(0x0F0)) // Plug and play 0xF0.
#define PNP_REG_IO_DEF_VAL1 ((USHORT)(0x0F1)) // Plug and play 0xF1.
//
// CRYSTAL ISA PACKET PAGE STRUCTURE FOR MEMORY MAPPED I/O.
//
//
// Following is the structure for the Plug and Play registers.
//
typedef struct _CRYSTAL_PNP_REGISTERS {
UCHAR RegActivate; // Packet page 0x330; Plug and play 0x30.
UCHAR RegIoRangeCheck; // Packet page 0x331; Plug and play 0x31.
UCHAR Reserved0[0x40-0x32];
UCHAR RegMbah0; // Packet page 0x340; Plug and play 0x40.
UCHAR RegMbal0; // Packet page 0x341; Plug and play 0x41.
UCHAR RegMcntl0; // Packet page 0x342; Plug and play 0x42.
UCHAR RegMrlh0; // Packet page 0x343; Plug and play 0x43.
UCHAR RegMrll0; // Packet page 0x344; Plug and play 0x44.
UCHAR Reserved1[0x48-0x45];
UCHAR RegMbah1; // Packet page 0x348; Plug and play 0x48.
UCHAR RegMbal1; // Packet page 0x349; Plug and play 0x49.
UCHAR RegMcntl1; // Packet page 0x34a; Plug and play 0x4a.
UCHAR Reserved2[0x60-0x4b];
UCHAR RegIObah0; // Packet page 0x360; Plug and play 0x60.
UCHAR RegIObal0; // Packet page 0x361; Plug and play 0x61.
UCHAR Reserved3[0x70-0x62];
UCHAR RegIrqs0; // Packet page 0x370; Plug and play 0x70.
UCHAR RegIrqts0; // Packet page 0x371; Plug and play 0x71.
UCHAR Reserved4[0x74-0x72];
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?