sa1100.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 494 行
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494 行
/* -*-C-*-
*
* $Revision: 1.2 $
* $Author: kwelton $
* $Date: 1999/10/25 21:40:55 $
*
* sa1100.h - StrongARM1100 definitions and macros
*
* Copyright (c) ARM Limited 1999.
* All Rights Reserved.
*/
#define READ_REGISTER_ULONG(reg) (*(volatile unsigned long * const)(reg))
#define WRITE_REGISTER_ULONG(reg, val) (*(volatile unsigned long * const)(reg)) = (val)
#define READ_REGISTER_USHORT(reg) (*(volatile unsigned short * const)(reg))
#define WRITE_REGISTER_USHORT(reg, val) (*(volatile unsigned short * const)(reg)) = (val)
#define READ_REGISTER_UCHAR(reg) (*(volatile unsigned char * const)(reg))
#define WRITE_REGISTER_UCHAR(reg, val) (*(volatile unsigned char * const)(reg)) = (val)
/*
* SA1100 defines
*/
#define EXT(d, b) ((((unsigned int)(d))>>(b))&1)
#define EXTV(d, hb, lb)\
(((((unsigned int)(d))>>(lb))&((((unsigned int)0xffffffff)<<(31-(hb)))>>((lb)+(31-(hb))))) & 0xffffffff)
/****** This has to change once ethernet is implemented. Kept for reference ****/
#define ETHERNET_BASE 0x3000
// The low bit of this word is stored in the FPGA. If set to a 1, it will assert
// the RESET pin of the 91C94.
#define SMC_HARD_RESET_REG (ETHERNET_BASE + 32)
// For debug ethernet routines, we set aside a chunk of memory for packet buffers
// if the IMGEBOOT variable is set (see config.bib).
#define EDBG_PHYSICAL_MEMORY_START ((DMA_PHYSICAL_BASE)+0x30000)
/********************************************************************************/
// Base Address for GLOBAL shared memory.
#define DMA_BUFFER_BASE 0xAC000000
#define DMA_PHYSICAL_BASE RAM1Base
// System Control Module Interrupt Controller Register Locations
#define IC_BASE 0xA9050000 /* SCM IC Base */
struct icreg {
int icip; // R
int icmr; // RW
int iclr; // RW
int icr_0x0C;
int icfp; //R
int icr_0x14;
int icr_0x18;
int icr_0x1C;
int icpr; // R
};
// SA1100 Interrupt controller bit positions
#define RTC_ALM 0x80000000
#define HZ_TIC 0x40000000
#define OS_TIMER3 0x20000000
#define OS_TIMER2 0x10000000
#define OS_TIMER1 0x08000000
#define OS_TIMER0 0x04000000
#define IC_DMA_CH5 0x02000000
#define IC_DMA_CH4 0x01000000
#define IC_DMA_CH3 0x00800000
#define IC_DMA_CH2 0x00400000
#define IC_DMA_CH1 0x00200000
#define IC_DMA_CH0 0x00100000
#define SERIAL_4B 0x00080000 // SSP
#define SERIAL_4A 0x00040000 // MCP
#define SERIAL_3 0x00020000 // UART
#define SERIAL_2 0x00010000 // HSSP/UART
#define SERIAL_1B 0x00008000 // UART Interrupt
#define SERIAL_1A 0x00004000 // SDLC Interrupt
#define SERIAL_0 0x00002000 // UDC
#define LCD_CTRL 0x00001000
#define GPIO_GRP 0x00000800
#define GPIO_10 0x00000400
#define GPIO_9 0x00000200
#define GPIO_8 0x00000100
#define GPIO_7 0x00000080
#define GPIO_6 0x00000040
#define GPIO_5 0x00000020
#define GPIO_4 0x00000010
#define GPIO_3 0x00000008
#define GPIO_2 0x00000004
#define GPIO_1 0x00000002
#define GPIO_0 0x00000001
// Memory control registers
#define MEM_CTRL_BASE MDCNFG
struct memreg {
int mdcnfg;
int mdcas0;
int mdcas1;
int mdcas2;
int msc0;
int msc1;
int mecr;
};
#define PCMCIA_SLOW 0xFFFFFFFF
#define PCMCIA_FAST 0x08840884
// System Control Module GPIO Register Locations
#define GPIO_BASE 0xA9040000 /* SCM GP BASE */
struct gpioreg {
int gplr; // R
int gpdr; // RW
int gpsr; // W
int gpcr; // W
int grer; // RW
int gfer; // RW
int gedr; // RW
int gafr; // RW
};
#define OST_BASE 0xA9000000
struct ostreg {
int osmr0;
int osmr1;
int osmr2;
int osmr3;
int oscr;
int ossr;
int ower;
int oier;
};
#define OSSR_M_M0 0x00000001
#define OSSR_M_M1 0x00000002
#define OSSR_M_M2 0x00000004
#define OSSR_M_M3 0x00000008
#define OIER_M_E0 0x00000001
#define OIER_M_E1 0x00000002
#define OIER_M_E2 0x00000004
#define OIER_M_E3 0x00000008
// Real time clock defines
#define RTC_BASE 0xA9010000
struct rtcreg{
int rtar;
int rcnr;
int rttr;
int pad;
int rtsr;
};
// RTC Status reg bits
#define RTC_AL 0x00000001 // Alarm detected
#define RTC_HZ 0x00000002 // 1 HZ rising edge detected
#define RTC_ALE 0x00000004 // Alarm interrupt enabled
#define RTC_HZE 0x00000008 // 1 HZ interrupt enabled
#define VIDEO_REAL_BASE 0xB0100000
#define LCD_REAL_BASE 0xB0100000
#define LCD_BASE 0xAB100000
#define VIDEO_BASE 0xAB100000
/* These are ordered according to the tests in Ashleys area */
/* They DO NOT match the current V2.0 spec as of 4-19-97 */
struct lcd_regs {
int Control0; /* LCCR0 */
int Status; /* LCSR */
int Reserved1; /* Pad */
int Reserved2; /* Pad */
int DMA1Base; /* DBAR1 */
int DMA1Current; /* DCAR1 */
int DMA2Base; /* DBAR2 */
int DMA2Current; /* DCAR2 */
int Control1; /* LCCR1 */
int Control2; /* LCCR2 */
int Control3; /* LCCR3 */
};
#define FRAME_BASE 0xAC007E00
#define FRAME_REAL_BASE (Ram1Base + 0x7E00)
struct FrameBuffer {
unsigned short palette [256];
unsigned char pixel[240][320];
int row,col;
};
// LCD Status Register
#define LCD_LFD 0x00000001
#define LCD_BAU 0x00000002
#define LCD_BER 0x00000004
#define LCD_ABC 0x00000008
#define LCD_IOL 0x00000010
#define LCD_IUL 0x00000020
#define LCD_IOU 0x00000040
#define LCD_IUU 0x00000080
#define LCD_OOL 0x00000100
#define LCD_OUL 0x00000200
#define LCD_OOU 0x00000400
#define LCD_OUU 0x00000800
/* LCD Control Register 0 Bits */
#define LCD0_M_LEN 0x00000001
#define LCD0_M_CMS 0x00000002
#define LCD0_M_SDS 0x00000004
#define LCD0_M_PAS 0x00000080
#define LCD0_M_BLE 0x00000100
#define LCD0_M_DPD 0x00000200
#define LCD0_M_FDD 0x000FF000
#define LCD0_V_LEN 0
#define LCD0_V_CMS 1
#define LCD0_V_SDS 2
#define LCD0_V_PAS 7
#define LCD0_V_BLE 8
#define LCD0_V_DPD 9
#define LCD0_V_FDD 12
/* LCD control Register 1 Bits */
#define LCD1_M_PPL 0x000003FF
#define LCD1_M_HSW 0x0000FC00
#define LCD1_M_ELW 0x00FF0000
#define LCD1_M_BLW 0xFF000000
#define LCD1_V_PPL 0
#define LCD1_V_HSW 10
#define LCD1_V_ELW 16
#define LCD1_V_BLW 24
/* LCD control Register 2 Bits */
#define LCD2_M_LPP 0x000003FF
#define LCD2_M_VSW 0x0000FC00
#define LCD2_M_EFW 0x00FF0000
#define LCD2_M_BFW 0xFF000000
#define LCD2_V_LPP 0
#define LCD2_V_VSW 10
#define LCD2_V_EFW 16
#define LCD2_V_BFW 24
/* LCD control Register 2 Bits */
#define LCD3_M_PCD 0x000000FF
#define LCD3_M_ACB 0x0000FF00
#define LCD3_M_API 0x000F0000
#define LCD3_M_VSP 0x00100000
#define LCD3_M_HSP 0x00200000
#define LCD3_M_PCP 0x00400000
#define LCD3_M_OEP 0x00800000
#define LCD3_V_PCD 0
#define LCD3_V_ACB 8
#define LCD3_V_API 16
#define LCD3_V_VSP 20
#define LCD3_V_HSP 21
#define LCD3_V_PCP 22
#define LCD3_V_OEP 23
struct sspreg {
int mccr;
int res1;
int mcdr0;
int mcdr1;
int mcdr2;
int res2;
int mcsr;
int res0x1C;
int res0x20;
int res0x24;
int res0x28;
int res0x2C;
int res0x30;
int res0x34;
int res0x38;
int res0x3C;
int res0x40;
int res0x44;
int res0x48;
int res0x4C;
int res0x50;
int res0x54;
int res0x58;
int res0x5C;
int sscr0;
int sscr1;
int ssppad0;
int ssdr;
int ssppad1;
int sssr;
};
/* SSP CR0 */
#define SSPCR0_M_DSS 0x0000000F
#define SSPCR0_M_FRF 0x00000030
#define SSPCR0_M_SSE 0x00000080
#define SSPCR0_M_SCR 0x0000FF00
#define SSPCR0_V_DSS 0
#define SSPCR0_V_FRF 4
#define SSPCR0_V_SSE 7
#define SSPCR0_V_SCR 8
/* SSP CR1 */
#define SSPCR1_M_RIM 0x00000001
#define SSPCR1_M_TIN 0x00000002
#define SSPCR1_M_LBM 0x00000004
#define SSPCR1_V_RIM 0
#define SSPCR1_V_TIN 1
#define SSPCR1_V_LBM 2
/* SSP status */
#define SSPSR_M_TNF 0x00000002
#define SSPSR_M_RNE 0x00000004
#define SSPSR_M_BSY 0x00000008
#define SSPSR_M_TFS 0x00000010
#define SSPSR_M_RFS 0x00000020
#define SSPSR_M_ROR 0x00000040
#define SSPSR_V_TNF 1
#define SSPSR_V_RNE 2
#define SSPSR_V_BSY 3
#define SSPSR_V_TFS 4
#define SSPSR_V_RFS 5
#define SSPSR_V_ROR 6
#define SSP_BASE 0xA8070000 // Has to be at 4K page boundary for virtual copy
// register structure is padded accordingly
struct mcpreg
{
int mccr;
int res1;
int mcdr0;
int mcdr1;
int mcdr2;
int res2;
int mcsr;
};
#define MCP_BASE 0xA8060000
// MCP Control Reg
#define MCP_MCE 0x00010000
#define MCP_ECS 0x00020000
#define MCP_ADM 0x00040000
#define MCP_TTM 0x00080000
#define MCP_TRM 0x00100000
#define MCP_ATM 0x00200000
#define MCP_ARM 0x00400000
#define MCP_LBM 0x00800000
#define MCP_ECP0 0x00000000
#define MCP_ECP1 0x01000000
#define MCP_ECP2 0x02000000
#define MCP_ECP3 0x03000000
// MCP Status Reg
#define MCP_ATS 0x00000001
#define MCP_ARS 0x00000002
#define MCP_TTS 0x00000004
#define MCP_TRS 0x00000008
#define MCP_ATU 0x00000010
#define MCP_ARO 0x00000020
#define MCP_TTU 0x00000040
#define MCP_TRO 0x00000080
#define MCP_ANF 0x00000100
#define MCP_ANE 0x00000200
#define MCP_TNF 0x00000400
#define MCP_TNE 0x00000800
#define MCP_CWC 0x00001000
#define MCP_CRC 0x00002000
#define MCP_ACE 0x00004000
#define MCP_TCE 0x00008000
#define PPC_BASE 0xA9060000
struct ppcreg
{
int ppdr;
int ppsr;
int ppar;
int psdr;
int ppfr;
};
#define PPAR_SPR 0x00040000
#define UART3_REAL_BASE 0x80050000
#define UART3_VBASE 0xA8050000
struct uart3 {
int utcr0;
int utcr1;
int utcr2;
int utcr3;
int RES1;
int utdr;
int RES2;
int utsr0;
int utsr1;
};
// Status Reg 1
#define UART_TBY 0x00000001
#define UART_RNE 0x00000002
#define UART_TNF 0x00000004
#define UART_PRE 0x00000008
#define UART_FRE 0x00000010
#define UART_ROR 0x00000020
// Status Reg 0
#define UART_TFS 0x00000001
#define UART_RFS 0x00000002
#define UART_RID 0x00000004
#define UART_RBB 0x00000008
#define UART_REB 0x00000010
#define UART_EIF 0x00000020
#define UART_CLEAR_ALL 0xFFFFFFFF
// Control Reg 3
#define UART_RXE 0x00000001
#define UART_TXE 0x00000002
#define UART_BRK 0x00000004
#define UART_RIM 0x00000008
#define UART_TIM 0x00000010
#define UART_LBM 0x00000020
#define UART_DISABL_ALL 0x00000000
//Control Reg 1
#define BAUD_HI 0x00000000
#define SERB_BAUD_RATE_MASK 0x00ff
// Common baud rates defined in platform.h, here are the odd ones:
#define ARM_BAUD_75 0xBFF
#define ARM_BAUD_150 0x5FF
#define ARM_BAUD_300 0x2FF
#define ARM_BAUD_600 0x17F
#define ARM_BAUD_3600 0x03F
#define ARM_BAUD_7200 0x01F
#define ARM_BAUD_12800 0x011
#define ARM_BAUD_23040 0x009
#define ARM_BAUD_28800 0x007
//Control Reg 0
#define UART_PE 0x00000001
#define UART_OES 0x00000002
#define UART_SBS 0x00000004
#define UART_DSS 0x00000008
#define UART_SCE 0x00000010
#define UART_RCE 0x00000020
#define UART_TCE 0x00000040
#define UART_N_8_1 0x00000008
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
/* EOF sa1100.h */
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