cache720t.s

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· S 代码 · 共 96 行

; -*-Asm-*-
;
; $Revision: 1.3 $
;   $Author: kwelton $
;     $Date: 2000/08/09 20:43:42 $
;
; Cache720t.s - cache control routines for an ARM720T processor
;
; Copyright (c) 1998 ARM Limited
; All Rights Reserved
;
        TEXTAREA

    LEAF_ENTRY OEMARMCacheMode
;++
; Routine Description:
;    Sets the C and B bits to be used to build page tables
;
; C and B bits are part of the page table entries and control write through vs.
; write back cache modes, cacheability, and write buffer use. Note that C 
; and B bit functionality is processor specific and different for the 720,
; 920, and SA1100. Consult the CPU hardware manual for the CPU
; in question before altering these bit configurations!!
; This default configuration (C=B=1)works on all current ARM CPU's and gives
: the following behaviour
; ARM720: write through, write buffer enabled
; ARM920: write back cache mode
; SA1100: write back, write buffer enabled
;
; The four valid options are:
;   ARM_NoBits      0x00000000
;   ARM_CBit        0x00000008
;   ARM_BBit        0x00000004
;   ARM_CBBits      0x0000000C
;
; Syntax:
;   DWORD OEMARMCacheMode(void);
;
; Arguments:
;   -- none --
;
; Return Value:
;  r0 must contain the desired C and B bit configuration. See description above
;  for valid bit patterns.
;
; Caution:
;  The value placed in r0 MUST be an immediate data value and NOT a predefined
;  constant. This function is called at a point in the boot cycle where the 
:  memory containing predefined constants has NOT been initialized yet.
;  --
        mov r0, #0x0c

    IF Thumbing
        bx  lr
    ELSE
        mov pc, lr
    ENDIF

;++
; Routine Description:
;    Flush and invalidate the TLB
;
; Syntax:
;       void TLBClear(void);
;
; Arguments:
;       -- none --
;
; Return Value:
;       -- none --
;--
        LEAF_ENTRY TLBClear
        mcr     p15, 0, r0, c8, c7, 0   ; flush I+D TLBs

    IF Thumbing
        bx  lr
    ELSE
        mov pc, lr                      ; return
    ENDIF


        LEAF_ENTRY  FlushDCache
        ALTERNATE_ENTRY FlushICache

        mcr p15, 0, r0, c7, c7, 0

    IF Thumbing
        bx  lr
    ELSE
        mov pc, lr          ; return
    ENDIF

    END

; EOF cache720t.s