target.s

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· S 代码 · 共 1,283 行 · 第 1/4 页

; -*-Asm-*-
;
; $Revision: 1.5 $
;   $Author: kwelton $
;     $Date: 2000/09/27 01:14:03 $
;
; Copyright (c) ARM Limited 1998, 1999.
; All Rights Reserved.
;

        SUBT    Integrator board description and Angel support > INTEGRATOR/target.s

        ; ---------------------------------------------------------------------
        ; This file defines the Integrator manifests and macros required
        ; to support the Angel world. It is not a complete description
        ; of the board, only the information necessary for Angel. It
        ; is envisaged that individual device drivers or application
        ; code will hold the necessary definitions for the other board
        ; features.
        ;
        ; NOTE: To help keep the main Angel source as generic as
        ; possible, heavy use is made of macros. However, it is likely
        ; that the use of macros will hide some very obvious and
        ; simple optimisations. If optimised Angel source is required,
        ; then a fixed target version should be created by the porting
        ; developer. The aim of Angel is to be as simple and quick to
        ; port as possible.
        ;
        ; ---------------------------------------------------------------------

      IF :DEF: OPT
        ASSERT  (listopts_s)
old_opt SETA    {OPT}
        OPT     (opt_off)       ; disable listing of include files
      ENDIF

        ; ---------------------------------------------------------------------

        IF :LNOT: :DEF: INTEGRATOR_target_s

                GBLL    INTEGRATOR_target_s
INTEGRATOR_target_s     SETL    {TRUE}

        ; ---------------------------------------------------------------------
        ; The "ROMonly" build variable controls whether the system
        ; being built supports a system where only ROM is mapped at
        ; zero, and RAM cannot be mapped there. i.e. where the ARM
        ; vectors are hard-wired in ROM. We create this variable
        ; un-conditionally, to ensure that if an attempt is made to
        ; define it elsewhere then a build error will occur.
        
                GBLL    ROMonly ; depends on target
ROMonly         SETL    {FALSE} ; {TRUE} if no RAM at zero


        INCLUDE platform.s
        GET     mmumacro.s

        ; ---------------------------------------------------------------------
        ; -- ANGEL and uHAL Support macros ------------------------------------
        ; ---------------------------------------------------------------------

        ; ------------------------------------------------------------------
        ; STEP_ONE
        ; --------
        ; First instruction.
        ; Normally LDR  PC, uHALip_ResetStart
        ; If the uHAL application is executing from a different address
        ; to the address it was built for (such as a system where 
        ; memory management hasn't been turned on yet), the first
        ; instruction may _have_ to be a branch relative:
        ; B     uHALir_ResetGo

        MACRO
        STEP_ONE
        LDR     PC, uHALip_ResetStart
        MEND

        ; ------------------------------------------------------------------
        ; CHECK_PRIMARY_CPU
        ; -----------------
        ; The Integrator/SDB hardware support multiple headers, however
        ; uHAL is not currently multiprocessor aware. If the platform
        ; supports multiple CPUs, platform-specific initialisation
        ; will be required before this block can be removed.

        MACRO
        CHECK_PRIMARY_CPU
        ; Load base address of header registers
        LDR     v1, =INTEGRATOR_HDR_BASE

        LDR     v1, [v1, #INTEGRATOR_HDR_STAT_OFFSET] ; Load HDR_STAT
        ANDS    v3, v1, #0xFF           ; Get header number, zero is primary
        CMPNE   v3, #0xFF               ; 0xFF = Invalid or no motherboard

        ; !!!!!!!!!!!!!!!!!!!!!!
        ; uHAL will not progress pass this point as it does not support
        ; multiprocessors.
        BNE     .
        ; !!!!!!!!!!!!!!!!!!!!!!

        MEND

        ; ------------------------------------------------------------------
        ; UNMAPROM
        ; --------
        ; Provide code to deal with mapping the reset ROM away from zero
        ; (if required).

        MACRO
$label  UNMAPROM        $w1,$w2

        LDR     $w1, =INTEGRATOR_HDR_CTRL
        LDR     $w2, [$w1]
        ORR     $w2, $w2, #4    ; Set REMAP bit
        STR     $w2, [$w1]

        MEND

        ; ---------------------------------------------------------------------
        ; STARTUPCODE             ** ANGEL SPECIFIC **
        ; -----------
        ; Provide code to deal with the main act of mapping the reset
        ; ROM away from zero (if required), and ensuring that the
        ; target I/O world is suitably clean before attempting to
        ; initialise the rest of Angel.
        ;
        ; NOTE:  do not use r4, that's $pos.
        ;
        
        MACRO
$label  STARTUPCODE     $w1,$w2,$pos,$ramsize

      IF {ENDIAN} = "big"
        ; Need to be in big-endian mode before any byte/half-word accesses
        MOV     $w1, #0
        SET_BIGEND      $w1
        WRMMU_STATE     $w1     ; Update control register
      ENDIF

        ; Okay, now initialise LEDs to a known state - off
        MOV     $w1, #0                 ; all off
        
        SET_LEDS        $w1, $w2

        ; Wait around to allow led pattern to be seen
        LDR     r0, =0x8000
L1
        SUBS    r0, r0, #1
        BNE     L1

      IF :DEF: FLASH_BOOT_LOADER
        ; Check which flash block is to be executed (and switch to it).
        BOOTLD  $w1, $w2

        ; We only return here if flash block 0 was selected.
      ENDIF             ; FLASH_BOOT_LOADER

        ; Initialise the DRAM (if present)
        ; NOTE: These macros have become so large that startrom.s cannot
        ;       handle local branches around STARTUPCODE. So we need to put
        ;       in an LTORG _inside_ this macro (with associated branch).
        ;vvvvvvvvvvvvvvv
        B       StartMem

        LTORG           ; Allows code using STARTUPCODE to do local loads

StartMem
        INIT_RAM        $w1, $w2, $ramsize

        DISABLE_INTS    $w1, $w2

        ; Finally, setup PCI
      IF uHAL_PCI = 1
        SETUP_PCI       $w1, $w2, r6, r7
      ENDIF

        MOV             $w1, #1                         ; 001, --Y
        DO_DEBUG        $w1, $w2

        MEND


        ; ---------------------------------------------------------------------
        ; RAM_REG
        ; -------
        ; ANGEL and uHAL macro to convert the memory size into a size mask for
        ; the DRAM_ADDR_SIZE registers. Looks for the LSB (since each array is
        ; a power of 2 in size) and returns the number of zero's bits which is
        ; the mask..
        ;       $w1 -> size of array (multiple of 1MB)
        ;       $w2 -> returns mask value

        MACRO
        RAM_REG $w1, $w2                ; Convert to DRAM_ADDR_SIZE mask
        MOV     $w2, #0
        CMP     $w1, $w2
        BEQ     L3                      ; Empty - nothing to do
L2
        ADD     $w2, $w2, #1
        TST     $w1, #1                 ; LSB set?
        MOV     $w1, $w1, LSR #1
        BEQ     L2                      ; No, try next shuffled down bit
L3
        MEND

        ; ------------------------------------------------------------------
        ; GOTO_ROM
        ; --------
        ; ANGEL and uHAL macro to switch from 0 to high alias of ROM. Some
        ; systems cannot just switch to High ROM, but must set up the MMU.

        MACRO
        GOTO_ROM        $w1, $w2

        ; Loading pc with uHALip_HiReset makes sure we're running from
        ; real rom, rather than a shadowed address.
        ;
        ; Make sure that the switch hasn't already happened (Multi ICE).
        LDR     $w1,=INTEGRATOR_HDR_CTRL
        LDR     $w2,[$w1]
        TST     $w2, #0x04

        ;
        ; XXX
        ;
        ; Some systems (e.g. WinCE) are built to copy themselves out
        ; of ROM, and execute from RAM. If that is so, then the linked
        ; address for uHALip_HiReset will be a RAM address - we can't
        ; load that into the PC, because we may not have copied ourselves
        ; down into RAM yet
        ;
    [ {FALSE}
        LDREQ   pc, =uHALip_HiReset
uHALip_HiReset
    |
        LDREQ   $w1, =FLASH_BASE
        ADDEQ   pc, pc, $w1

        ; NOP to account for pipelining in the add instruction above
        NOP
    ]

        LDR     $w1, =INTEGRATOR_HDR_CTRL
        LDR     $w2, [$w1]
        ORR     $w2, $w2, #4    ; Set REMAP bit
        STR     $w2, [$w1]

        MEND



        ; ---------------------------------------------------------------------
        ; VALIDATE_PROCESSOR
        ; ------------------
        ;
        ; Macro to validate that the software and hardware are compatible.
        ;
        MACRO
        VALIDATE_PROCESSOR      $w1, $w2, $w3

        CHECK_VENDOR    $w1, $w2
        BNE     L4

        ; Checks to see if the h/w and s/w match.
        CHECK_CPUID     $w1, $w2
        BEQ     L5

        ;
        ; If we get here then there is a problem.  We will flash the
        ; red LED on the motherboard to indicate this.
        ;
L4      LDR     $w3, =INTEGRATOR_RTC_BASE
        LDR     $w1, [$w3]
        ANDS    $w1, $w1, #1
        MOVNE   $w1, #RED_LED

        SET_LEDS $w1, $w2 

        B       L4
L5

        MEND

        ;---------------------------------------------------------------------
        ; SETUP_ASYNC_CLOCKS
        ; ------------------
        ;
        ; Set up asynchronous clocking (eg. core and memory clocks different)
        ;
        MACRO
        SETUP_ASYNC_CLOCKS      $w1, $w2

        ; Read bit field in HDR_OSC to determine how to do this.
        LDR     $w1, =INTEGRATOR_HDR_BASE
        LDR     $w2, [$w1, #INTEGRATOR_HDR_OSC_OFFSET]
        AND     $w2, $w2, #(3 :SHL: 23)
        CMP     $w2, #(1 :SHL: 23)
        BNE     L5a

        ; If HDR_OSC indicates, set implementation-specific bits in MMU reg
        WRCLK_EnableClockSW     $w2
L5a
        ; Set in HDR_CTRL
        LDRLT   $w2, [$w1, #INTEGRATOR_HDR_CTRL_OFFSET]
        ORRLT   $w2, $w2, #0xC0
        STRLT   $w2, [$w1, #INTEGRATOR_HDR_CTRL_OFFSET]

        MEND


        ; ---------------------------------------------------------------------
        ; SETUP_DEFAULT_CLOCKS
        ; --------------------
        ;
        ; Macro to set up the clock settings on Integrator depending
        ; on what type of header card we are running on.
        ;
        ; Core clock must always be greater than memory clock.
        ;
        ; These are -