sdbtest.c

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C语言 代码 · 共 1,249 行 · 第 1/4 页

	if(dwNextHostWindowBoundary == 0)
		ProcessCommands();
#endif


		while( dwCurPCIAddr < dwNextHostWindowBoundary && dwCurPCIAddr < dwLastPCIAddr ) {
#if 1
		if ( (dwCurPCIAddr & 0x0000FFFF) == 0) {
			static char ledstr[80];
			ToStr((unsigned)dwCurPCIAddr, ledstr);
			Write_LED_Data(ledstr, (unsigned)dwCurPCIAddr);
		}
#endif 1
			/* Determine new verification and write data */
			switch( bTestPhase ) {
			case 1:
				dwWriteData = 0;
				break;
			case 2:
				dwVerificationData = 0;
				dwWriteData = dwCurPCIAddr;
				break;
			case 3:
				dwVerificationData = dwCurPCIAddr;
				dwWriteData = ~dwCurPCIAddr;
				break;
			}
			/* Use the specified access width	*/
			switch( bAccessWidth ) {
			case 8:
				if (fDoVerification) {
MY_DELAY
					bReadData = *pvbData;
					if (bReadData != (BYTE)dwVerificationData) {
TRIGGER;
						DbgPrintf( "TestRAMRegion(%d) - ERROR: PCI Addr 0x%08lX, Wrote 0x%02X, Read 0x%02X\n",
							bTestPhase, dwCurPCIAddr, (BYTE)dwVerificationData, bReadData );
						return 1;
					}
				}
MY_DELAY
				*pvbData++ = (BYTE)dwWriteData;
				if (fDoVerification) {
MY_DELAY
					bReadData = *pvbData;
					if (bReadData != (BYTE)(dwVerificationData >> 8)) {
TRIGGER;
						DbgPrintf( "TestRAMRegion(%d) - ERROR: PCI Addr 0x%08lX, Wrote 0x%02X, Read 0x%02X\n",
							bTestPhase, dwCurPCIAddr + 1, (BYTE)(dwVerificationData >> 8), bReadData );
						return 1;
					}
				}
MY_DELAY
				*pvbData++ = (BYTE)(dwWriteData >> 8);
				if (fDoVerification) {
MY_DELAY
					bReadData = *pvbData;
					if (bReadData != (BYTE)(dwVerificationData >> 16)) {
TRIGGER;
						DbgPrintf( "TestRAMRegion(%d) - ERROR: PCI Addr 0x%08lX, Wrote 0x%02X, Read 0x%02X\n",
							bTestPhase, dwCurPCIAddr + 2, (BYTE)(dwVerificationData >> 16), bReadData );
						return 1;
					}
				}
MY_DELAY
				*pvbData++ = (BYTE)(dwWriteData >> 16);
				if (fDoVerification) {
MY_DELAY
					bReadData = *pvbData;
					if (bReadData != (BYTE)(dwVerificationData >> 24)) {
TRIGGER;
						DbgPrintf( "TestRAMRegion(%d) - ERROR: PCI Addr 0x%08lX, Wrote 0x%02X, Read 0x%02X\n",
							bTestPhase, dwCurPCIAddr + 3, (BYTE)(dwVerificationData >> 24), bReadData );
						return 1;
					}
				}
MY_DELAY
				*pvbData++ = (BYTE)(dwWriteData >> 24);
				break;
			case 16:
				if (fDoVerification) {
#if 0	// Works fine with 8 MB
if( 0 == ( (unsigned)pvwData % 0x10000) )  DbgPrintf("Reading 0x%x...\n", pvwData);
#endif 1
MY_DELAY
					wReadData = *pvwData;
					if (wReadData != (WORD)dwVerificationData) {
TRIGGER;
						DbgPrintf( "TestRAMRegion(%d) - ERROR: PCI Addr 0x%08lX, Wrote 0x%04X, Read 0x%04X\n",
							bTestPhase, dwCurPCIAddr, (WORD)dwVerificationData, wReadData );
						return 1;
					}
				}
MY_DELAY
				*pvwData++ = (WORD)dwWriteData;
				if (fDoVerification) {
MY_DELAY
					wReadData = *pvwData;
					if (wReadData != (WORD)(dwVerificationData >> 16)) {
TRIGGER;
						DbgPrintf( "TestRAMRegion(%d) - ERROR: PCI Addr 0x%08lX, Wrote 0x%04X, Read 0x%04X\n",
							bTestPhase, dwCurPCIAddr + 2, (WORD)(dwVerificationData >> 16), wReadData );
						return 1;
					}
				}
MY_DELAY
				*pvwData++ = (WORD)(dwWriteData >> 16);
				break;
			case 32:
				if (fDoVerification) {
MY_DELAY
					dwReadData = *pvdwData;
					if (dwReadData != dwVerificationData) {
TRIGGER;
						DbgPrintf( "TestRAMRegion(%d) - ERROR: PCI Addr 0x%08lX, Wrote 0x%08lX, Read 0x%08lX\n",
							bTestPhase, dwCurPCIAddr, dwVerificationData, dwReadData );
						return 1;
					}
				}
// 				DbgPrintf(".");
MY_DELAY
				*pvdwData++ = dwWriteData;
				break;
			}
			dwCurPCIAddr += 4;
		}
	}
DbgPrintf("TTR returning 0\n");

	return 0;

} /* TestRAMRegion() */



/* This routine will initialize the i960 on the RIO.  The given parameters	*/
/*	for windows to allow prefetchable, non-prefetchable and I/O accesses	*/
/*	onto RIO are specified.  Setting the limit register to a value less		*/
/*	than the base register will close that window entirely.  Also, the base	*/
/*	address for the shared RAM is specified.								*/
int InitI960(	PCIDevAddrRec *pRIO, 
				DWORD dwPrefetchMemBaseAddr, DWORD dwPrefetchMemLimit,
				DWORD dwNonPrefetchMemBaseAddr, DWORD dwNonPrefetchMemLimit,
				DWORD dwIOBaseAddr, DWORD dwIOLimitAddr,
				DWORD dwSharedRAMBase ) {

	WORD wPCIStatus;

	DbgPrintf( "+InitI960: bBusNo=%d, bDevNo=%d\n", pRIO->bBusNo, pRIO->bDevNo);
	DbgPrintf("dwPMemB=0x%x, L=0x%x, NonPMemB=0x%x, L=0x%x, IoB=0x%x, L=0x%x, ShRamB=0x%x\n", 
		dwPrefetchMemBaseAddr, dwPrefetchMemLimit, dwNonPrefetchMemBaseAddr, dwNonPrefetchMemLimit,
		dwIOBaseAddr, dwIOLimitAddr, dwSharedRAMBase);

	/* Added by Naresh for Debugging */
#ifdef NKCH
	{
		// Clear PCI Bridge Status
		ClearPCIBridgeStatus( pRIO );
	}
#endif 1
	/* Set Cache Line Size Register	*/
	/*	Cache line fills, as done by Memory Write and Invalidate, are disabled by a value of 0 */
	OEM_WriteConfigByte( pRIO->bBusNo, pRIO->bDevNo, 0, 0x0C, 0 );

	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		DbgPrintf("GetPCIBridgeStatus returned 0x%x, pRIO->bParentDevNo=0x%x\n", wPCIStatus, pRIO->bParentDevNo);
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Cache Line Size Register\n" );
		PrintPCIError( wPCIStatus );
		ProcessCommands();
		return 1;
	}

	/* Set Primary Latency Timer Register	*/
	/*	Set to 32 clocks to allow reasonable bursts without bus hogging	*/
	OEM_WriteConfigByte( pRIO->bBusNo, pRIO->bDevNo, 0, 0x0D, 32 );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Primary Latency Timer Register\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}
	/* Set Secondary Latency Timer Register	*/
	/*	Set to 32 clocks to allow reasonable bursts without bus hogging	*/
	OEM_WriteConfigByte( pRIO->bBusNo, pRIO->bDevNo, 0, 0x1B, 32 );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Secondary Latency Timer Register\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}

	/* Set I/O base and limit registers.  Note that the bridge only supports I/O addresses	*/
	/*	in the lowest 64K range, meaning that for an access to get through the bridge,		*/
	/*	bits [31:16] must be 0.  Bits [7:4] of this byte wide register programs bits		*/
	/*	[15:12] of the address range since the lower four bits of the i960 register are		*/
	/*	hardwired to 0.  The same ranging rules as for the memory spaces apply.				*/
	OEM_WriteConfigByte( pRIO->bBusNo, pRIO->bDevNo, 0, 0x1C, (BYTE)((0x0000F000 & dwIOBaseAddr) >> 8) );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write I/O Base Address\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}
	OEM_WriteConfigByte( pRIO->bBusNo, pRIO->bDevNo, 0, 0x1D, (BYTE)((0x0000F000 & dwIOLimitAddr) >> 8) );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write I/O Limit Address\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}

	/* Set the Non-Prefetchable Memory Base address, only bits 31:20 can be set so	*/
	/*	the entire memory range must be at least 1 Megabyte.						*/
	OEM_WriteConfigWord( pRIO->bBusNo, pRIO->bDevNo, 0, 0x20, (WORD)(dwNonPrefetchMemBaseAddr >> 16) );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Non-Prefetchable Memory Base Address\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}
	/* Set the Non-Prefetchable Memory Limit address, only bits 31:20 can be set and the low	*/
	/*	bits are assumed to be all 1's.  If the limit is strictly less than the base, then		*/
	/*	nothing will be forwarded.																*/
	OEM_WriteConfigWord( pRIO->bBusNo, pRIO->bDevNo, 0, 0x22, (WORD)(dwNonPrefetchMemLimit >> 16) );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Non-Prefetchable Memory Limit Address\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}

	/* Set the Prefetchable Memory Base address, only bits 31:20 can be set so	*/
	/*	the entire memory range must be at least 1 Megabyte.					*/
	OEM_WriteConfigWord( pRIO->bBusNo, pRIO->bDevNo, 0, 0x24, (WORD)(dwPrefetchMemBaseAddr >> 16) );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Prefetchable Memory Base Address\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}
	/* Set the Prefetchable Memory Limit address, only bits 31:20 can be set and the low bits	*/
	/*	are assumed to be all 1's.  If the limit is strictly less than the base, then nothing	*/
	/*	will be forwarded.																		*/
	OEM_WriteConfigWord( pRIO->bBusNo, pRIO->bDevNo, 0, 0x26, (WORD)(dwPrefetchMemLimit >> 16) );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Prefetchable Memory Limit Address\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}

	/************************************************************************************/
	/* Everything in the section between these bars is i960RP specific.					*/

	/* Set i960 Control Register	*/
	OEM_WriteConfigWord( pRIO->bBusNo, pRIO->bDevNo, 0, 0x3E, 0x0003 );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write i960 Control Register\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}

	/* Set Extended i960 Control Register											*/
	OEM_WriteConfigWord( pRIO->bBusNo, pRIO->bDevNo, 0, 0x40, 0x0010 );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Extended i960 Control Register\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}

	/* Set Secondary Arbitration Control Register						*/
	/*	Enable secondary arbiter and give all devices equal priority	*/
	OEM_WriteConfigDword( pRIO->bBusNo, pRIO->bDevNo, 0, 0x4C, 0x00010000 );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Secondary Arbitration Control Register\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}

	/* Set PCI Interrupt Routing Control Register									*/
	/*	Set to route all secondary PCI interrupts to the primary PCI bus and not to	*/
	/*	the i960 core.																*/
	OEM_WriteConfigDword( pRIO->bBusNo, pRIO->bDevNo, 0, 0x50, 0 );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write PCI Interrupt Routing Select Register\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}

	/* Set Secondary Address Decode Register									*/
	/*	Set up inverse decoding for all secondary to primary transactions and	*/
	/*	disable private memory space.											*/
	OEM_WriteConfigWord( pRIO->bBusNo, pRIO->bDevNo, 0, 0x5C, 0 );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Secondary Address Decode Register\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}

	/* Set Primary & Secondary Inbound ATU Base Address Register	*/
	OEM_WriteConfigDword( pRIO->bBusNo, pRIO->bDevNo, 1, 0x10, dwSharedRAMBase );
	if ((wPCIStatus = GetPCIBridgeStatus( pRIO )) != 0) {
		ClearPCIBridgeStatus( pRIO );
		DbgPrintf( "InitI960() - ERROR: Can't Write Primary Inbound ATU Base Address Register\n" );
		PrintPCIError( wPCIStatus );
		return 1;
	}