oemdbg.c

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C语言 代码 · 共 155 行

/******************************************************************************
 * File: 	oemdbg.c
 * Author: 	Naresh Gupta ([e-mail])
 * Date: 	Thursday, March 04, 1999
 * Organization: Hitachi Semiconductor America, Inc.
 * Purpose:	Debug routines.
 ******************************************************************************/

/******************************************************************************
 * Notes :-

 * This file does nothing since all this stuff has already been done in 
 * debug.c in the bootloader and SDBTESTS will be a part of the bootloader.
 ****************************************************************************/
#define OEM_DEBUG_READ_NODATA   (-1)
#if 1
void OEMWriteDebugByte(unsigned char bData);
int OEMReadDebugByte(void);
void OEM_DbgOutputInit( void ) {
	// Do nothing as the serial port has already been initialized.
	return;
}

int OEM_DbgReadByte( void ) {
	char c;
	while ((c=OEMReadDebugByte())==OEM_DEBUG_READ_NODATA);
	return c;
}

void OEM_DbgWriteByte( unsigned char bData ) {
	OEMWriteDebugByte(bData);
	return;
}
#else
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995, 1996, 1997, 1998  Microsoft Corporation

Module Name:  
    oemdbg.c

Abstract:  
    Function implementations for debug communication manipulation.

Functions:


Notes: 

--*/
#include "common.h"
#include "oem.h"


/* Global pointer to the base address for the serial controller.  In this case		*/
/*	it is a 16550 compatible chip.													*/
volatile BYTE *pvbSerReg;


/* This routine initializes the serial controller for use by DbgPrintf().  It sets	*/
/*	it to 38400 baud, no parity, 8 data bits and 1 stop bit.						*/
void OEM_DbgOutputInit( void ) {

	DWORD dwDivisor;

	/* Initialize secondary PCI I/O window so that I can access the onboard PC87560	*/
	/* Enable Bus Mastering on the secondary PCI segment for the ATU through the	*/
	/*	Primary ATU Command Register												*/
	*(volatile WORD *)0x00001298 = 0x0157;

	/* Set the secondary outbound I/O Window Register PCI base address to 0	*/
	*(volatile DWORD *)0x0000126C = 0;

	/* I can now access the lower 64K of PCI I/O address space by accessing the 64K	*/
	/*	processor address range beginning at 0x90010000.  I will use the standard	*/
	/*	0x02F8 as the base address for the serial port on the CPU card.  Note that	*/
	/*	this address space is independent of the address space used to access the	*/
	/*	backplane peripherals and so there is no possibility of a collision with	*/
	/*	any backplane addresses.													*/
	pvbSerReg = (volatile BYTE *)(0x90010000 + 0x02F8);

	/* Enable on-board debug serial	*/
	*(volatile DWORD *)0x000012A8 = 0x00040158;
	*(volatile DWORD *)0x000012B0 = 0x000A0024;

	/* Set baud rate by setting Divisor Latches	*/
	/*  Must set DLAB bit	*/
	pvbSerReg[SER_LCR] |= 0x80;
	/* Set baud rate to 38400 */
	dwDivisor = 1843200UL / 38400 / 16UL;
	pvbSerReg[SER_DLL] = (BYTE)dwDivisor;
	pvbSerReg[SER_DLM] = (BYTE)(dwDivisor >> 8);
	/* Clear DLAB bit	*/
	pvbSerReg[SER_LCR] &= 0x7F;

	/* Set up the Line Control Register */
	/* Set number of data bits to 8, 1 stop bit, no parity	*/
	pvbSerReg[SER_LCR] = 3;

	/* Reset FIFOs, set for interrupt when 1 byte has been received	*/
	pvbSerReg[SER_FCR] = 0x07;

	/* Disable all interrupts for polled mode only	*/
	pvbSerReg[SER_IER] = 0x00;

	/* Assert Request To Send and Data Terminal Ready					*/
	/*  Also, specific to the PC87307, bit 3 enables interrupt output	*/
	pvbSerReg[SER_MCR] |= 0x03;

} /* OEM_DbgInitDebugOutput */



/* This routine will return a single byte from the serial port if there is one	*/
/*	available.  If there are no bytes available, then it returns -1.			*/
int OEM_DbgReadByte( void ) {

	BYTE bStatus;

	bStatus = pvbSerReg[SER_LSR];
	/* If there is data available	*/
	if (bStatus & 0x01)
		return pvbSerReg[SER_RBR];
	else
		return -1;

} /* OEM_DbgReadByte() */



/* This routine will write a single byte to the serial port.  Note that it does	*/
/*	not return until the byte has been passed to the serial controller.			*/
void OEM_DbgWriteByte( BYTE bData ) {

	/* Wait until the Transmitter Holding Register (THRE) indicates that there is	*/
	/*	room in the FIFO															*/
	while(!(pvbSerReg[SER_LSR] & 0x20));

	/* Check the host machine's Data Set Ready.  If it has been de-asserted, then	*/
	/*	wait until it has been re-asserted.											*/
	/* In this way, the host can tell us to stop sending data.  Of course, we may	*/
	/*	already have up to 16 bytes in the FIFO that will be sent regardless of the	*/
	/*	state of this signal, but the host must be able to deal with that.  The DSR	*/
	/*	line just says, stop putting new stuff in the FIFO.							*/
	while(!(pvbSerReg[SER_MSR] & 0x20));

	/* Send the character	*/
	pvbSerReg[SER_THR] = bData;

} /* OEM_DbgWriteByte()	*/
#endif