mq200init.cpp

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C++ 代码 · 共 137 行

///////////////////////////////////////////////////////////////////////
////  Initialization sequence ...
////  1. Setup DCR00R - use whatever is in the registry.           ////
////     This is supposed to be required for NEC and StrongARM     ////
////  2. Enter D0 state from reset.                                ////
////  3. Verify if right MediaQ chip ID.                           ////
////  4. Setup PMU.                                                ////
////  5. Setup MIU.                                                ////
////  6. Setup FPI
////  7. set up GC1 to drive 640x480x8 60Hz simul LCD and CRT mode
///////////////////////////////////////////////////////////////////////

#if 1
#include <standalone.h>
#include "mqstruc.h"
#include "modes.h"
#include "mqhw2.h"
#include "mqmacro.h"
#include "panels.h"
#endif 0

#if 0
#define dcREG(id,data)			(REG32(DC_BASE,id)=data)
#endif 0
void

unsigned *m_pMMIO				0xA5000000;

SetMQMode(void)
{

	RETAILMSG(1,( TEXT("MQGC::SetMQMode\r\n")));

	dcREG(DC_0, ulDC0); 		//Always from OSC and used to drive MIU/GE
									//50Mhz=0x0EB22A2A, 83MHz=0x0EF2082A

	Sleep(40);
	pciREG(PCI_PM_CNTL_STATUS, ENTER_D0);
	Sleep(80);

	CHECK_IF_STATE_D(0); 		//Make sure in a stable state
								//- shouldn't be necessary here !!!

	RETAILMSG(1,( TEXT("MQGC::SetMQMode - in D0 state now ...\r\n")));

	if ( pciREAD(PCI_VENDOR_DEVICE) != MQ200_DEVICE )
	{
		RETAILMSG(1,( TEXT("MQGC::ID=%08x ...\r\n"),pciREAD(PCI_VENDOR_DEVICE)));
		RETAILMSG(1,( TEXT("MQGC::SetMQMode - invalid Device ID ...\r\n")));
		return;
	}

	if ( m_ulBPP >= 8UL )
	{
		//Enable GE if >= 8bpp.  Use PLL1 as initial clk src for GE.
		pmuREG(PM_MISC, (GE_ENABLE | GE_BY_PLL1) );
	}

	//To initialize MIU bloc,:
	//
	miuREG(MIU_CONTROL1, DRAM_RESET_DISABLE);
	Sleep(100);

	miuREG(MIU_CONTROL1, 0x00);
	Sleep(50);

	//ulMIU2 = 0x40EA0020;	// PLL1=MIU,trun on bit 30 for rev1a
	ulMIU2 = 0x00EA0086;	// PLL1=MIU,trun on bit 30 for rev1a
	//ulMIU2 = 0x00EA0087;	// PLL2=MIU,trun on bit 30 for rev1a
	//ulMIU3 = 0x6d0ddc00;
	ulMIU3 = 0x6d6aabff;
	ulMIU5 = 0x10d;
	ulMIU4 = 0x00000001;

	miuREG(MIU_CONTROL2, ulMIU2);
	miuREG(MIU_CONTROL3, ulMIU3);
	// MIU REG 5 MUST BE PROGRAMMED BEFORE MIU REG 4
	miuREG(MIU_CONTROL5, ulMIU5);
	miuREG(MIU_CONTROL4, ulMIU4);
	Sleep(10);   									//Step 2

	miuREG(MIU_CONTROL1, MIU_ENABLE | MIU_RESET_DISABLE);
	Sleep(50);

	// MIU init complete ...

	// Set up gc1 stride and start address
	gc1REG(IW1_STRIDE, 		ulIW_StrideXX);
	gc1REG(IW1_START_ADDR,	ulIW_StartAddrXX);

	// flat panel registers
	if (m_nDSTNFBControl != -1) 		// DSTN is used in the system
  		fpREG(DSTN_FB_CONTROL, m_nDSTNFBControl);
	
	//Set up the rest of flat panel registers - depend on panel type
	fpREG(FP_CONTROL, 		m_pFPControl->ulFPControl);
	fpREG(FP_PIN_CONTROL,	m_pFPControl->ulFPPinControl);
	fpREG(FP_GPO_CONTROL,	OemInfo.ulFPGPO);
	fpREG(FP_GPIO_CONTROL,	OemInfo.ulFPGPIO);
	fpREG(STN_CONTROL,		m_pFPControl->ulSTNControl);
	fpREG(PWM_CONTROL,		ulTemp);

	//FRC is NOT needed for TFT panel
	if ( (m_pFPControl->ulFPControl & FP_TYPE_MASK) != FP_TYPE_TFT )
	{
		int		i;
		for ( i = 0; i < FRC_PATTERN_CNT; i++ )
  			fpREG((FRC_PATTERN + i * uBUSW), FRCControlData[0].ulFRCPattern[i]);
		for ( i = 0; i < FRC_WEIGHT_CNT; i++ )
  			fpREG((FRC_WEIGHT + i * uBUSW), FRCControlData[0].ulFRCWeight[i]);
	}

	// Set up CRT control register - don't enable yet
	gc1REG(GC1_CRT_CONTROL, BLANK_PED_ENABLE);
	
	// GC timing
	gcREG(ulGCBase, HW1_CONTROL,		ulHW_ControlLCD);
	gcREG(ulGCBase, VW1_CONTROL,		ulVW_ControlLCD);
	gcREG(ulGCBase, HD1_CONTROL, m_pFPControl->ulHD);
	gcREG(ulGCBase, VD1_CONTROL, m_pFPControl->ulVD);
	gcREG(ulGCBase, HS1_CONTROL, m_pFPControl->ulHS);
	gcREG(ulGCBase, VS1_CONTROL, m_pFPControl->ulVS);

	// 640x480x8 60Hz, use pll3 to driver LCD and CRT at simultaneous mode
	// PLL3=0x00a30930 (25.175MHz)
	gcREG(ulGCBase,GC1_CONTROL, ulTemp);

#ifdef NKCH
	HW_Enable_LCD( GC1 );
	HW_Enable_CRT( GC1 );

	Done.
	see other files for reference regarding data structure, timing etc.
#endif NKCH

}