init.src

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

;
;  Copyright(c) 1998,1999 SIC/Hitachi,Ltd.
;
;	Module Name:
;
;		init.src
;
;	Revision History:
;
;		26th April 1999		Released
;		25th June  1999		Changed bootloader region size
;

        .list OFF
        .include "kxshx.h"
        .include "shx.inc"
        .include "boot.inc"
        .list ON

;Stack:  .equ    h'8C151000
Stack:  .equ    h'8C020000

        .import _main

;/*****************************************************************************
;*      FUNCTION :              StartUp()
;*      DESCRIPTION :   The initial starting point of the system
;*      INPUTS :                None - we are branched to from the reset vector
;*      OUTPUTS :               None, we branch to the main()
;*      CAUTIONS :              We are operating in Clock Mode 3.  There are a lot
;*                              of things that can change based on the position of
;*                              some DIP Switches so keep up with the comments
;*
;*    o Constructors are not initialized.  They aren't used by the bootloader.
;*
;*    o exit is not called.  There is no stdio library, etc., to close.
;*
;*    The bootloader is configured to run from RAM in memory section P1 (cached)
;*    but the SH-4 boots in FLASH in section P2 (uncached).  Thus, the initial
;*    memory setup code below (up to the call to _main) must be position
;*    independent.
;*
;* Arguments:
;*
;*    None; we are branched to, not called.
;*
;* Return Value:
;*
;*    None; there is nothing to return to.
;*
;*************************************************************************************
        LEAF_ENTRY _StartUp

        mov.l   #TM_SR,r0		; release mask etc
        ldc     r0,sr
;
        mov.l   #h'00000000,r0
        ldc     r0,vbr
;
        mov.l   #CPG_WTCSR,r1
        mov.w   #ZERO_TME,r0
        mov.w   r0,@r1
        nop
;
        mov.l   #CPG_WTCNT,r1
        mov.w   #COUNT_INIT,r0
        mov.w   r0,@r1
        nop

;-------------------------------------------------------

        mov.l   #CPG_FRQCR,r1	;
        mov.w   #CPG_FRQCR_CLOCK,r0
;        mov.w   #h'0e13,r0		;   I:B:P =  6 : 2 : 1
;        mov.w   #h'0e23,r0		;   I:B:P =  6 : 1 : 1
        mov.w   r0,@r1

;-------------------------------------------------------

        mov.l   #BSC_BCR1,r1	;
	.aif SDRAM_MODULE eq h'01
        mov.l   #BSC_BCR1_MEMORY_MAP_SDRAM,r0
	.aelse
        mov.l   #BSC_BCR1_MEMORY_MAP_EDO,r0
	.aendi
        mov.l   r0,@r1

;-------------------------------------------------------

        mov.l   #BSC_BCR2,r1	;
        mov.w   #BSC_BCR2_BUS_WIDTHS,r0
        mov.w   r0,@r1

;-------------------------------------------------------

        mov.l   #BSC_WCR1,r1	;
        mov.l   #BSC_WCR1_IDLE_STATES,r0
        mov.l   r0,@r1

;-------------------------------------------------------

        mov.l   #BSC_WCR2,r1	;
        mov.l   #BSC_WCR2_WAIT_STATES,r0		
        mov.l   r0,@r1

;-------------------------------------------------------

        mov.l   #BSC_WCR3,r1	;
        mov.l   #BSC_WCR3_WAIT_INSERTED,r0
        mov.l   r0,@r1

;-------------------------------------------------------

		mov.l	#BSC_MCR,r1		;
	.aif SDRAM_MODULE eq h'01
		mov.l	#BSC_MCR_MEM_TYPE_SDRAM,r0	; MCR.MRSET = 0
		mov.l	r0,@r1
		mov.l	#h'FF940190,r1	; BSC_SDMR3
		mov.b	r1,@r1
	.aelse
		mov.l	#BSC_MCR_MEM_TYPE_EDO,r0
		mov.l	r0,@r1			;
	.aendi

;-------------------------------------------------------

        mov.l   #BSC_PCR,r1		;
        mov.w   #BSC_PCR_WAIT_INSERTED,r0
        mov.w   r0,@r1

;-------------------------------------------------------

        mov.l   #BSC_RTCSR,r1   ;
        mov.w   #BSC_RTCSR_SETTINGS,r0
        mov.w   r0,@r1

;-------------------------------------------------------

        mov.l   #BSC_RTCNT,r1   ;
        mov.w   #BSC_RTCNT_START,r0
        mov.w   r0,@r1

;-------------------------------------------------------

        mov.l   #BSC_RTCOR,r1   ;
        mov.w   #BSC_RTCOR_MAX_COUNT,r0
        mov.w   r0,@r1

;-------------------------------------------------------

	.aif	SDRAM_MODULE eq h'01
MCR_timer:
        mov.l   #h'0000fff0,r0		; dummy auto refresh cycle
MCR_loop:
        dt      r0
        bf      MCR_loop

        mov.l   #BSC_MCR,r1		;
        mov.l   #BSC_MCR_SDRAM_MRSET,r0		; MCR.MRSET = 1
        mov.l   r0,@r1
		mov.l	#h'FF940190,r1	; BSC_SDMR3
		mov.b	r1,@r1
	.aendi

;-------------------------------------------------------

; The bootloader is linked to run from RAM but is initially installed in FLASH
; at the SH-4's boot address.  Now that memory has been configured, copy the
; entire bootloader image to RAM.
;
; N.B.  The bootloader's region size must agree with boot.bib's declaration of
; it.

        mov.l   #0x140000/4,r0           ; Size of bootloader's region in words
        mov.l   #0xa0000000,r1          ; Cached alias of loader's FLASH addr
        mov.l   #0xac010000,r2          ; Cached alias of loader's RAM address
CopyLoop:
        mov.l   @r1,r3                  ; Load next bootloader word
        add     #-1,r0                  ; 1 less word to copy
        mov.l   r3,@r2                  ; Store next bootloader word
        cmp/eq  #0,r0                   ; Done?
        add     #4,r1                   ; 4 more bytes loaded
        bf/s    CopyLoop                ;   (more of Done?)
         add     #4,r2                  ; 4 more bytes stored

; Flush then enable the cache in copy-back mode.

CCN_CCR_FLUSH:		.equ	CCN_CCR_ICI | CCN_CCR_OCI
CCN_CCR_ENABLE:		.equ	CCN_CCR_ICE | CCN_CCR_OCE | CCN_CCR_CB

        mov.l   #CCN_CCR,r1
        mov.l   #CCN_CCR_FLUSH,r0		; Flush the cache
        mov.l   r0,@r1
        mov     #CCN_CCR_ENABLE,r0		; Enable the cache
        mov.l   r0,@r1

        nop
        nop
        nop

        mov     #Stack,r15              ; Set up a stack

; The bootloader is linked to run in section P1 (cached) but is started at
; reset in section P2 (uncached).  Now that memory has been configured and the
; cache turned on, the jsr to _main (an absolute address) also branches from
; section P2 to section P1, effectively enabling the cache at the same time.

        mov.l   #_main,r0               ; Call main

        jsr     @r0                     ; Should never return
        nop

HaltLoop:
        bra     HaltLoop                ; If return, stop with LEDs = 0x0f
        nop

    ENTRY_END _StartUp

;++
;
; void Launch(
;    unsigned long pFunc
;    )
;
; Routine Description:
;
;    This function launches the program at pFunc.  The expectation is that
;    the launched program never returns.
;
; Arguments:
;
;    pFunc (r4) - Supplies the address of the program to launch.
;
; Return Value:
;
;    None; the launched program never returns.
;
;--

    LEAF_ENTRY _Launch
    jmp     @r4
    nop
    ENTRY_END _Launch

    LEAF_ENTRY _LaunchExisting
    jmp     @r4
    nop
    ENTRY_END _LaunchExisting
    
INDEX_REG_R0:           .equ 0
INDEX_REG_R1:           .equ 4
INDEX_REG_R2:           .equ 8
INDEX_REG_R3:           .equ 12
INDEX_REG_R4:           .equ 16
INDEX_REG_R5:           .equ 20
INDEX_REG_R6:           .equ 24
INDEX_REG_R7:           .equ 28
INDEX_REG_GBR:          .equ 32
INDEX_REG_MACH:         .equ 36
INDEX_REG_MACL:         .equ 40
INDEX_REG_PC:           .equ 44
INDEX_REG_PR:           .equ 48
INDEX_REG_SR:           .equ 52
INDEX_REG_SPR:          .equ 56
INDEX_REG_SSR:          .equ 60


; DEBUGTIME .equ 0                  ; Disable debug timing
DEBUGTIME   .equ 1                  ; Enable debug timing


    .aif DEBUGTIME
LoopCount .equ 50000000
    
    LEAF_ENTRY _Time1
    mov     #LoopCount,r0
T1Loop:
    dt      r0
    bf      T1Loop
    rts
     nop
    ENTRY_END _Time1
    
    LEAF_ENTRY _Time2
    mov     #LoopCount,r0
T2Loop:
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    dt      r0
    bf      T2Loop
    rts
     nop
    ENTRY_END _Time2
    
    LEAF_ENTRY _Time3
    mov     #LoopCount,r0
T3Loop:
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    nop
    dt      r0
    bf      T3Loop
    rts
     nop
    ENTRY_END _Time3
    .aendi

    .end