disasm.c

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C语言 代码 · 共 738 行 · 第 1/2 页

#include "platform.h"
#include "dis.h"

const sh_opcode_info sh_table[] =
{
  {"ADD",
   {A_IMM, A_REG_N},
   {HEX_7, REG_N, IMM_8}},
  {"ADD",
   {A_REG_M, A_REG_N},
   {HEX_3, REG_N, REG_M, HEX_C}},
  {"ADDC",
   {A_REG_M, A_REG_N},
   {HEX_3, REG_N, REG_M, HEX_E}},
  {"ADDV",
   {A_REG_M, A_REG_N},
   {HEX_3, REG_N, REG_M, HEX_F}},
  {"AND",
   {A_IMM, A_R0},
   {HEX_C, HEX_9, IMM_8}},
  {"AND",
   {A_REG_M, A_REG_N},
   {HEX_2, REG_N, REG_M, HEX_9}},
  {"AND.B",
   {A_IMM, A_R0_GBR},
   {HEX_C, HEX_D, IMM_8}},
  {"BRA",
   {A_BDISP12},
   {HEX_A, BRANCH_12}},
  {"BSR",
   {A_BDISP12},
   {HEX_B, BRANCH_12}},
  {"BT",
   {A_BDISP8},
   {HEX_8, HEX_9, BRANCH_8}},
  {"BF",
   {A_BDISP8},
   {HEX_8, HEX_B, BRANCH_8}},
  {"BT/S",
   {A_BDISP8},
   {HEX_8, HEX_D, BRANCH_8}},
  {"BF/S",
   {A_BDISP8},
   {HEX_8, HEX_F, BRANCH_8}},
  {"CLRMAC",
   {0},
   {HEX_0, HEX_0, HEX_2, HEX_8}},
  {"CLRS",
   {0},
   {HEX_0, HEX_0, HEX_4, HEX_8}},
  {"CLRT",
   {0},
   {HEX_0, HEX_0, HEX_0, HEX_8}},
  {"CMP/EQ",
   {A_IMM, A_R0},
   {HEX_8, HEX_8, IMM_8}},
  {"CMP/EQ",
   {A_REG_M, A_REG_N},
   {HEX_3, REG_N, REG_M, HEX_0}},
  {"CMP/GE",
   {A_REG_M, A_REG_N},
   {HEX_3, REG_N, REG_M, HEX_3}},
  {"CMP/GT",
   {A_REG_M, A_REG_N},
   {HEX_3, REG_N, REG_M, HEX_7}},
  {"CMP/HI",
   {A_REG_M, A_REG_N},
   {HEX_3, REG_N, REG_M, HEX_6}},
  {"CMP/HS",
   {A_REG_M, A_REG_N},
   {HEX_3, REG_N, REG_M, HEX_2}},
  {"CMP/PL",
   {A_REG_N},
   {HEX_4, REG_N, HEX_1, HEX_5}},
  {"CMP/PZ",
   {A_REG_N},
   {HEX_4, REG_N, HEX_1, HEX_1}},
  {"CMP/STR",
   {A_REG_M, A_REG_N},
   {HEX_2, REG_N, REG_M, HEX_C}},
  {"DIV0S",
   {A_REG_M, A_REG_N},
   {HEX_2, REG_N, REG_M, HEX_7}},
  {"DIV0U",
   {0},
   {HEX_0, HEX_0, HEX_1, HEX_9}},
  {"DIV1",
   {A_REG_M, A_REG_N},
   {HEX_3, REG_N, REG_M, HEX_4}},
  {"EXTS.B",
   {A_REG_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_E}},
  {"EXTS.W",
   {A_REG_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_F}},
  {"EXTU.B",
   {A_REG_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_C}},
  {"EXTU.W",
   {A_REG_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_D}},
  {"JMP",
   {A_IND_N},
   {HEX_4, REG_N, HEX_2, HEX_B}},
  {"JSR",
   {A_IND_N},
   {HEX_4, REG_N, HEX_0, HEX_B}},
  {"LDC",
   {A_REG_N, A_SR},
   {HEX_4, REG_N, HEX_0, HEX_E}},
  {"LDC",
   {A_REG_N, A_GBR},
   {HEX_4, REG_N, HEX_1, HEX_E}},
  {"LDC",
   {A_REG_N, A_VBR},
   {HEX_4, REG_N, HEX_2, HEX_E}},
  {"LDC",
   {A_REG_N, A_SSR},
   {HEX_4, REG_N, HEX_3, HEX_E}},
  {"LDC",
   {A_REG_N, A_SPC},
   {HEX_4, REG_N, HEX_4, HEX_E}},
  {"LDC",
   {A_REG_N, A_REG_B},
   {HEX_4, REG_N, REG_B, HEX_E}},
  {"LDC.L",
   {A_INC_N, A_SR},
   {HEX_4, REG_N, HEX_0, HEX_7}},
  {"LDC.L",
   {A_INC_N, A_GBR},
   {HEX_4, REG_N, HEX_1, HEX_7}},
  {"LDC.L",
   {A_INC_N, A_VBR},
   {HEX_4, REG_N, HEX_2, HEX_7}},
  {"LDC.L",
   {A_INC_N, A_SSR},
   {HEX_4, REG_N, HEX_3, HEX_7}},
  {"LDC.L",
   {A_INC_N, A_SPC},
   {HEX_4, REG_N, HEX_4, HEX_7}},
  {"LDC.L",
   {A_INC_N, A_REG_B},
   {HEX_4, REG_N, REG_B, HEX_7}},
  {"LDS",
   {A_REG_N, A_MACH},
   {HEX_4, REG_N, HEX_0, HEX_A}},
  {"LDS",
   {A_REG_N, A_MACL},
   {HEX_4, REG_N, HEX_1, HEX_A}},
  {"LDS",
   {A_REG_N, A_PR},
   {HEX_4, REG_N, HEX_2, HEX_A}},
  {"LDS.L",
   {A_INC_N, A_MACH},
   {HEX_4, REG_N, HEX_0, HEX_6}},
  {"LDS.L",
   {A_INC_N, A_MACL},
   {HEX_4, REG_N, HEX_1, HEX_6}},
  {"LDS.L",
   {A_INC_N, A_PR},
   {HEX_4, REG_N, HEX_2, HEX_6}},
  {"LDTLB",
   {0},
   {HEX_0, HEX_0, HEX_3, HEX_8}},
  {"MAC.W",
   {A_INC_M, A_INC_N},
   {HEX_4, REG_N, REG_M, HEX_F}},
  {"MOV",
   {A_IMM, A_REG_N},
   {HEX_E, REG_N, IMM_8}},
  {"MOV",
   {A_REG_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_3}},
  {"MOV.B",
   {A_REG_M, A_IND_R0_REG_N},
   {HEX_0, REG_N, REG_M, HEX_4}},
  {"MOV.B",
   {A_REG_M, A_DEC_N},
   {HEX_2, REG_N, REG_M, HEX_4}},
  {"MOV.B",
   {A_REG_M, A_IND_N},
   {HEX_2, REG_N, REG_M, HEX_0}},
  {"MOV.B",
   {A_DISP_REG_M, A_R0},
   {HEX_8, HEX_4, REG_M, IMM_4}},
  {"MOV.B",
   {A_DISP_GBR, A_R0},
   {HEX_C, HEX_4, IMM_8}},
  {"MOV.B",
   {A_IND_R0_REG_M, A_REG_N},
   {HEX_0, REG_N, REG_M, HEX_C}},
  {"MOV.B",
   {A_INC_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_4}},
  {"MOV.B",
   {A_IND_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_0}},
  {"MOV.B",
   {A_R0, A_DISP_REG_M},
   {HEX_8, HEX_0, REG_M, IMM_4}},
  {"MOV.B",
   {A_R0, A_DISP_GBR},
   {HEX_C, HEX_0, IMM_8}},
  {"MOV.L",
   {A_REG_M, A_DISP_REG_N},
   {HEX_1, REG_N, REG_M, IMM_4BY4}},
  {"MOV.L",
   {A_REG_M, A_IND_R0_REG_N},
   {HEX_0, REG_N, REG_M, HEX_6}},
  {"MOV.L",
   {A_REG_M, A_DEC_N},
   {HEX_2, REG_N, REG_M, HEX_6}},
  {"MOV.L",
   {A_REG_M, A_IND_N},
   {HEX_2, REG_N, REG_M, HEX_2}},
  {"MOV.L",
   {A_DISP_REG_M, A_REG_N},
   {HEX_5, REG_N, REG_M, IMM_4BY4}},
  {"MOV.L",
   {A_DISP_GBR, A_R0},
   {HEX_C, HEX_6, IMM_8BY4}},
  {"MOV.L",
   {A_DISP_PC, A_REG_N},
   {HEX_D, REG_N, PCRELIMM_8BY4}},
  {"MOV.L",
   {A_IND_R0_REG_M, A_REG_N},
   {HEX_0, REG_N, REG_M, HEX_E}},
  {"MOV.L",
   {A_INC_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_6}},
  {"MOV.L",
   {A_IND_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_2}},
  {"MOV.L",
   {A_R0, A_DISP_GBR},
   {HEX_C, HEX_2, IMM_8BY4}},
  {"MOV.W",
   {A_REG_M, A_IND_R0_REG_N},
   {HEX_0, REG_N, REG_M, HEX_5}},
  {"MOV.W",
   {A_REG_M, A_DEC_N},
   {HEX_2, REG_N, REG_M, HEX_5}},
  {"MOV.W",
   {A_REG_M, A_IND_N},
   {HEX_2, REG_N, REG_M, HEX_1}},
  {"MOV.W",
   {A_DISP_REG_M, A_R0},
   {HEX_8, HEX_5, REG_M, IMM_4BY2}},
  {"MOV.W",
   {A_DISP_GBR, A_R0},
   {HEX_C, HEX_5, IMM_8BY2}},
  {"MOV.W",
   {A_DISP_PC, A_REG_N},
   {HEX_9, REG_N, PCRELIMM_8BY2}},
  {"MOV.W",
   {A_IND_R0_REG_M, A_REG_N},
   {HEX_0, REG_N, REG_M, HEX_D}},
  {"MOV.W",
   {A_INC_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_5}},
  {"MOV.W",
   {A_IND_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_1}},
  {"MOV.W",
   {A_R0, A_DISP_REG_M},
   {HEX_8, HEX_1, REG_M, IMM_4BY2}},
  {"MOV.W",
   {A_R0, A_DISP_GBR},
   {HEX_C, HEX_1, IMM_8BY2}},
  {"MOVA",
   {A_DISP_PC, A_R0},
   {HEX_C, HEX_7, PCRELIMM_8BY4}},
  {"MOVT",
   {A_REG_N},
   {HEX_0, REG_N, HEX_2, HEX_9}},
  {"MULS",
   {A_REG_M, A_REG_N},
   {HEX_2, REG_N, REG_M, HEX_F}},
  {"MUL.L",
   {A_REG_M, A_REG_N},
   {HEX_0, REG_N, REG_M, HEX_7}},
  {"MULU",
   {A_REG_M, A_REG_N},
   {HEX_2, REG_N, REG_M, HEX_E}},
  {"NEG",
   {A_REG_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_B}},
  {"NEGC",
   {A_REG_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_A}},
  {"NOP",
   {0},
   {HEX_0, HEX_0, HEX_0, HEX_9}},
  {"NOT",
   {A_REG_M, A_REG_N},
   {HEX_6, REG_N, REG_M, HEX_7}},
  {"OR",
   {A_IMM, A_R0},
   {HEX_C, HEX_B, IMM_8}},
  {"OR",
   {A_REG_M, A_REG_N},
   {HEX_2, REG_N, REG_M, HEX_B}},
  {"OR.B",
   {A_IMM, A_R0_GBR},
   {HEX_C, HEX_F, IMM_8}},
  {"PREF",
   {A_IND_N},
   {HEX_0, REG_N, HEX_8, HEX_3}},
  {"ROTCL",
   {A_REG_N},
   {HEX_4, REG_N, HEX_2, HEX_4}},
  {"ROTCR",
   {A_REG_N},
   {HEX_4, REG_N, HEX_2, HEX_5}},
  {"ROTL",
   {A_REG_N},
   {HEX_4, REG_N, HEX_0, HEX_4}},
  {"ROTR",
   {A_REG_N},
   {HEX_4, REG_N, HEX_0, HEX_5}},
  {"RTE",
   {0},
   {HEX_0, HEX_0, HEX_2, HEX_B}},
  {"RTS",
   {0},
   {HEX_0, HEX_0, HEX_0, HEX_B}},
  {"SETS",
   {0},
   {HEX_0, HEX_0, HEX_5, HEX_8}},
  {"SETT",
   {0},
   {HEX_0, HEX_0, HEX_1, HEX_8}},
  {"SHAD",
   {A_REG_M, A_REG_N},
   {HEX_4, REG_N, REG_M, HEX_C}},
  {"SHLD",
   {A_REG_M, A_REG_N},
   {HEX_4, REG_N, REG_M, HEX_D}},
  {"SHAL",
   {A_REG_N},
   {HEX_4, REG_N, HEX_2, HEX_0}},
  {"SHAR",
   {A_REG_N},
   {HEX_4, REG_N, HEX_2, HEX_1}},
  {"SHLL",
   {A_REG_N},
   {HEX_4, REG_N, HEX_0, HEX_0}},
  {"SHLL16",
   {A_REG_N},
   {HEX_4, REG_N, HEX_2, HEX_8}},
  {"SHLL2",
   {A_REG_N},
   {HEX_4, REG_N, HEX_0, HEX_8}},
  {"SHLL8",
   {A_REG_N},
   {HEX_4, REG_N, HEX_1, HEX_8}},
  {"SHLR",
   {A_REG_N},
   {HEX_4, REG_N, HEX_0, HEX_1}},
  {"SHLR16",
   {A_REG_N},
   {HEX_4, REG_N, HEX_2, HEX_9}},
  {"SHLR2",
   {A_REG_N},
   {HEX_4, REG_N, HEX_0, HEX_9}},
  {"SHLR8",
   {A_REG_N},
   {HEX_4, REG_N, HEX_1, HEX_9}},
  {"SLEEP",