startup.src
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· SRC 代码 · 共 692 行 · 第 1/2 页
SRC
692 行
;/***************************************************************************
; File: startup.src
; Author : Naresh Gupta (nkgupta@hotmail.com)
; Purpose: This file defines the modules StartUp, and Out_LED
; Copyright (c) Hitachi Semiconductor America Inc.
;***************************************************************************/
.list ON
;//****************************************************************************
;// User Modifiable parameters
;//****************************************************************************
;//****************************************************************************
;// If FINE_TUNE is 1, the tuned values are used while booting from Flash.
;// Else the slower values are used.
;// This is just to make sure that the system is not mis-behaving due to
;// Tuned numbers
;//****************************************************************************
FINE_TUNE .equ 1
;/***************************************************************************
;* If RETAIN_BSC_SETTINGS is set, then when the image is booting from RAM,
;* the BSC is not overwritten. Rather, whatever values that were present
;* at system boot are used for Windows CE Bootup.
;***************************************************************************/
RETAIN_BSC_SETTINGS .equ 1
;/****************************************************************************
;;* Check whether the platform is defined.
;;****************************************************************************/
.aif SH_PLATFORM eq 0
Error: No platform defined. Please define the environment variable
Error: SH_PLATFORM to one of: S1, ASPEN, KEYWEST.
.aendi
;/****************************************************************************
;;* S1 specific stuff.
;;****************************************************************************/
.aif SH_PLATFORM eq PLATFORM_S1
;;// S1 has SDRAM on it.
SDRAM_ON .equ 1
ALPHA_LED .equ h'A3C60000
FRQCR_VAL .equ h'0e13 ; I:B:P = 6 : 1 : 1
.aif SDRAM_ON eq h'01
BCR1_VAL .equ h'00000009
MCR_VAL .equ h'8008221D
.aelse
BCR1_VAL .equ h'00000011
MCR_VAL .equ h'1802601C
.aendi
BCR2_VAL .equ h'2A3C
WCR1_VAL .equ h'11111111
WCR2_VAL .equ h'6DB667F3
WCR3_VAL .equ h'00040000
PCR_VAL .equ h'0000
RTCSR_VAL .equ h'a509
RTCNT_VAL .equ h'a500
RTCOR_VAL .equ h'a510
.aendi
;/****************************************************************************
;;* Aspen specific stuff.
;;****************************************************************************/
.aif SH_PLATFORM eq PLATFORM_ASPEN
.aif FINE_TUNE eq 0
;// Non Fine-tuned values.
FRQCR_VAL .equ h'0e13 ; I:B:P = 6 : 1 : 1
BCR1_VAL .equ h'80300009 ; h'80300008 ; BIT 21 = 1; BIT 20 = 1
BCR2_VAL .equ h'D7cc
WCR1_VAL .equ h'77777777
WCR2_VAL .equ h'FFFE6F7F ;;// FFFE6F67: Serial, parallel downloads work fine. A0: 6 WS, But cannot boot from Flash
;;// FFFE6F7F: File downloads thru serial port fail.
;;// FFFE6F6F: Everything seems fine.
WCR3_VAL .equ h'07777777 ; h'00000000 ; h'07777777
MCR_VAL .equ h'400a001C ; h'400a0014
MCR_VAL_1 .equ h'000a0014 ; Precharge
MCR_VAL_2 .equ h'400a001C ; h'400a0014 ; MRSET
PCR_VAL .equ h'5FFF ; h'0912
RTCSR_VAL .equ h'a594 ; h'a58c
RTCNT_VAL .equ h'a500
RTCOR_VAL .equ h'a511 ; h'a575
WAIT_200US .equ (1200 * 80)
ASPEN_BSC_SDMR3 .equ (BSC_SDMR3_COOKIE+BSC_SDMR3_190)
.aelse ;// FINE_TUNE eq 0
;// Fine-tuned values.
FRQCR_VAL .equ h'0e13 ; I:B:P = 6 : 1 : 1
BCR1_VAL .equ h'80300009 ; h'80300008 ; BIT 21 = 1; BIT 20 = 1
BCR2_VAL .equ h'6b3c ; S1 sets Area 5, 6 as 8 bit while i set them as 16 bit. check this out.
WCR1_VAL .equ h'77730642
WCR2_VAL .equ h'FFFE4D77 ;;// FFFE6F67: Serial, parallel downloads work fine. A0: 6 WS, But cannot boot from Flash
;;// FFFE6F7F: File downloads thru serial port fail.
;;// FFFE6F6F: Everything seems fine.
WCR3_VAL .equ h'07700000 ; h'00000000 ; h'07777777
MCR_VAL .equ h'4009001C ; h'400a0014
MCR_VAL_1 .equ h'00090014 ; Precharge
MCR_VAL_2 .equ h'4009001C ; h'400a0014 ; MRSET
PCR_VAL .equ h'5FFF ; h'0912
RTCSR_VAL .equ h'a594 ; h'a58c
RTCNT_VAL .equ h'a500
RTCOR_VAL .equ h'a511 ; h'a575
WAIT_200US .equ (1200 * 80)
ASPEN_BSC_SDMR3 .equ (BSC_SDMR3_COOKIE+BSC_SDMR3_110)
.aendi ;// FINE_TUNE eq 0
.aendi ;// SH_PLATFORM eq PLATFORM_ASPEN
;/****************************************************************************
;;* BigSur specific stuff
;;****************************************************************************/
.aif SH_PLATFORM eq PLATFORM_BIGSUR
.aif FINE_TUNE eq 0
;// Non Fine-tuned values.
FRQCR_VAL .equ h'0e13 ; I:B:P = 6 : 1 : 1
BCR1_VAL .equ h'80300009 ; h'80300008 ; BIT 21 = 1; BIT 20 = 1
BCR2_VAL .equ h'D7cc
WCR1_VAL .equ h'77777777
WCR2_VAL .equ h'FFFE6F7F ;;// FFFE6F67: Serial, parallel downloads work fine. A0: 6 WS, But cannot boot from Flash
;;// FFFE6F7F: File downloads thru serial port fail.
;;// FFFE6F6F: Everything seems fine.
WCR3_VAL .equ h'07777777 ; h'00000000 ; h'07777777
MCR_VAL .equ h'400a001C ; h'400a0014
MCR_VAL_1 .equ h'000a0014 ; Precharge
MCR_VAL_2 .equ h'400a001C ; h'400a0014 ; MRSET
PCR_VAL .equ h'5FFF ; h'0912
RTCSR_VAL .equ h'a594 ; h'a58c
RTCNT_VAL .equ h'a500
RTCOR_VAL .equ h'a511 ; h'a575
WAIT_200US .equ (1200 * 80)
BIGSUR_BSC_SDMR3 .equ (BSC_SDMR3_COOKIE+BSC_SDMR3_190)
.aelse ;// FINE_TUNE eq 0
;// Make changes here for BigSur ~~~~~
;// Fine-tuned values.
FRQCR_VAL .equ h'0e13 ; I:B:P = 6 : 1 : 1
BCR1_VAL .equ h'80300009 ; h'80300008 ; BIT 21 = 1; BIT 20 = 1
BCR2_VAL .equ h'6BFC ; S1 sets Area 5, 6 as 8 bit while i set them as 16 bit. check this out.
WCR1_VAL .equ h'77772642
WCR2_VAL .equ h'FFF66CFF ;;// FFFE6F67: Serial, parallel downloads work fine. A0: 6 WS, But cannot boot from Flash
;;// FFFE6F7F: File downloads thru serial port fail.
;;// FFFE6F6F: Everything seems fine.
WCR3_VAL .equ h'00000000 ; h'00000000 ; h'07777777
MCR_VAL .equ h'501A61B4 ; h'400a0014
MCR_VAL_1 .equ h'101A61B4 ; Precharge
MCR_VAL_2 .equ h'501A61B4 ; h'400a0014 ; MRSET
PCR_VAL .equ h'5FFF ; h'0912
RTCSR_VAL .equ h'a594 ; h'a58c
RTCNT_VAL .equ h'a500
RTCOR_VAL .equ h'a526 ; h'a575
WAIT_200US .equ (1200 * 80)
BIGSUR_BSC_SDMR3 .equ (BSC_SDMR3_COOKIE + h'00C8) ;;// Naresh: Could not understand this value. Copied from CMON
.aendi ;// FINE_TUNE eq 0
.aendi ;// SH_PLATFORM eq PLATFORM_BIGSUR
;//****************************************************************************
;// Which tests to carry out.
;//****************************************************************************
;// TEST1: It is carried on as soon as control transfers to the boot vector.
;// It needs ALPHA_LED to be set. This test would print incrementing
;// values from 30('1') to 39('9') to the LED.
TEST1 .equ 0
;//****************************************************************************
;// Use Operand Cache (OC) as RAM or use SDRAM ?
;//****************************************************************************
;// USE_OC_RAM should be defined as 1 if you want to use 8k OC (Operand Cache)
;// as RAM
USE_OC_RAM .equ 0
;//****************************************************************************
;// End of Modifiable parameters
;//****************************************************************************
;; Pick up the value of Stack from boot.bib.
;; (Address A + Address B)
.aif USE_OC_RAM eq 0
Stack: .equ h'8c200000
.aelse
Stack: .equ h'7c003000
.aendi
;/*****************************************************************************
;* Function: Startup
;* Synopsis: Initialize the cpu and jump to _main. It gets control at location
;* cpu boot vector (0xA0000000) and does initialization of FRQCR,
;* BCRx, WCRx, etc.
;* Input : None
;* Output : None
;* Notes :
;/****************************************************************************/
LEAF_ENTRY _StartUp
mova strt10, r0
mov r0, r1 ; Save the address of strt10 to find out
; the region of execution later on
mov #h'A0000000, r2 ; moves from section P1(cached) to P2 (uncached)
or r2, r0
jmp @r0 ; jumps to strt10 in section P2
nop
.align 4
strt10:
;//****************************************************************************
;// IF USE_OC_RAM is 1, then setup 8k of the OC to be used as RAM
;// This RAM would be a contiguous 8k block from 7c001000 - 7c002fff
;// Else set CCR to 0.
;//****************************************************************************
.aif USE_OC_RAM eq 1
mov.l #CCN_CCR, r0 ; Address of CCR
mov.l #h'000000A3, r1 ; IC, OC Enable, Write Through, OCRA
mov.l r1, @r0
.aelse
mov.l #CCN_CCR, r0
mov.l #H'00000808,r1 ; Invalidate and Disable Cache.
mov.l r1,@r0
.aendi
;;// Just put 8 nops after modifying CCR.
nop
nop
nop
nop
nop
nop
nop
nop
mov.l #ALPHA_LED, r8
mov.l #h'41, r7
mov.l r7, @r8
;//****************************************************************************
;// Run TEST1 if TEST1 is set as 1.
;//****************************************************************************
.aif TEST1 eq 1
;* First test is to show values from 0 to FF on the Alpha LED.
test1:
mov.l #h'00000030, r5 ;; Starting value to Write to Alpha LED
mov.l #h'00000033, r6 ;; Last value to be written to Alpha LED
loop_test1:
mov.b r5, @r8
add #h'1, r5
;* Put in a delay. otherwise the leds change too fast.
mov.l #h'00010000, r3
del_test1:
dt r3
bf del_test1
cmp/eq r5, r6
bf loop_test1
.aendi
;//****************************************************************************
;// End of TEST1
;//****************************************************************************
;/*****************************************************************************
;* Should BSC settings be retained in case of RAM boot.
;*****************************************************************************/
.aif RETAIN_BSC_SETTINGS eq 1
;//***************************************************************************
;// Flash image is at address: 80000000
;// Ram image is at address : 8c000000
;//****************************************************************************
mova DummyLabel, r0
mov.l #h'0F000000, r1
tst r0, r1
;// If r0 & r1 == 0 (T<-1), then it is Flash, Else it is RAM
bf Done_Set_IO_Registers
nop
.align 4
.aendi ;// RETAIN_BSC_SETTINGS
DummyLabel:
mov.l #BSC_BCR1,r1
mov.l #BCR1_VAL, r0
mov.l r0,@r1
mov.l #h'43, r7
mov.l r7, @r8
;//////////////////////////////////////////////////////////////////////////////
;//* Platform specific initialization for ASPEN
;//////////////////////////////////////////////////////////////////////////////
.aif SH_PLATFORM eq PLATFORM_ASPEN
mov.l #h'00000000,r0
ldc r0,vbr
mov.l #h'41, r7
mov.l r7, @r8
;-------------------------------------------------------
mov.l #h'42, r7
mov.l r7, @r8
mov.l #BSC_BCR1,r1
mov.l #BCR1_VAL, r0
mov.l r0,@r1
mov.l #h'43, r7
mov.l r7, @r8
;-------------------------------------------------------
mov.l #BSC_BCR2,r1
mov.l #BCR2_VAL, r0
mov.w r0,@r1
mov.l #h'44, r7
mov.l r7, @r8
;-------------------------------------------------------
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?