fw_org.src

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· SRC 代码 · 共 291 行

;
;  Copyright(c) 1998,1999 SIC/Hitachi,Ltd.
;
;	Module Name:
;
;		fw.src
;
;	Revision History:
;
;		26th April 1999		Released
;		14th April 1999		Modified (for HD64464)
;
	.include "kxshx.h"
	.include "boot.inc"
	.include "platform.inc"
	.include "shx.inc"
	.include "oalintr.inc"

	.section .text,code

	.align	4

	.export	_OEMExtraCCR
_OEMExtraCCR:	.data.l		h'105

	.import	KernelStart
	.import	_AlarmYear

;/*****************************************************************************
;*      FUNCTION :              StartUp()
;*      DESCRIPTION :   The initial starting point of the system
;*      INPUTS :                None - we are branched to from the reset vector
;*      OUTPUTS :               None, we branch to the main()
;******************************************************************************

	LEAF_ENTRY _StartUp

	mova	strt10, r0
	mov		#h'20000000, r2			; moves from section P1(cached) to P2 (uncached)
	or		r2, r0
	jmp		@r0					; jumps to strt10 in section P2
	nop

	.align	4

strt10:	

	mov.l	#LED_DISCRETE, r8		; Set up the WRITE_LEDS macro	

	mov.l	#TM_SR, r0				; release mask etc
	ldc		r0, sr

	; the very fist thing is to initialize the Watch Dog timer.

	mov		#CPG_WTCSR, r1
	mov		#ZERO_TME, r0
	mov.w   r0, @r1					; Set TME bit of WTCSR to 0 
	mov		#SET_CKS, r0
	mov.w   r0, @r1					; Set type of clock count to use in WTCSR
	mov		#CPG_WTCNT, r1
	mov		#COUNT_INIT, r0
	mov.w   r0, @r1					; Set initial value for counter in WTCNT
	
	; When the FRQCR is modified, it creates unstability in the PLL.  For this
	; reason, when FRQCR is modified, the CPU shuts off.  The Watchdog timer
	; can be programed to cause a wake-up of the system.  Currently that wake-up
	; interval is 0.  See section 10.9.2 in the SH4 manual.  

	.aif WITHOUT_BOOTLOADER eq h'01
		mov.l   #CPG_FRQCR, r1
		mov.w	#CPG_FRQCR_CLOCK, r0
		mov.w	r0, @r1
	.aendi

	; Now we need to set up the SH4's Bus State controller based on our platform's
	; memory map.  
	; BCR1 sets the types of memory that are being used.
	; BCR2 is used to set the bus widths of all of the memory areas.  All Bus
	; Widths are defined in boot.inc
	; Program the SH-4's bus state controller according platform memory architecture.

	mov		#BSC_BCR1, r2				

	.aif SDRAM_MODULE eq h'01
		mov		#BSC_BCR1_MEMORY_MAP_SDRAM, r1		
	.aelse
		mov		#BSC_BCR1_MEMORY_MAP_EDO, r1		
	.aendi

	mov.l	r1, @r2					

	mov		#BSC_BCR2, r2	
	mov		#BSC_BCR2_BUS_WIDTHS, r0		; Set bus width for each area
	.aif ENABLE_HD64464 eq h'01
	mov		#BSC_BCR2_A4SZ_32,r1
	or		r1,r0							; Set bus width of Area4 as 32 bit
	.aendi
	mov.w	r0, @r2

	mov		#BSC_WCR1, r2					; Set number of idle states
	mov		#BSC_WCR1_IDLE_STATES, r1		; Areas 6-0 and DACK device Inter Cycle all 1 idle state
	mov.l	r1, @r2							
	
	mov		#BSC_WCR2, r2					; Set number of wait states
	mov		#BSC_WCR2_WAIT_STATES, r1		
	mov.l	r1, @r2							; Area 1 is set 15 wait, others 3 wait

	mov		#BSC_WCR3,r2					; Set cycles insert and data hold time states
	mov		#BSC_WCR3_WAIT_INSERTED, r1		
	mov.l	r1,@r2							; All area 1 cycle inset and 1 data hold

	mov		#BSC_MCR,r2						; Set memory control,

	.aif SDRAM_MODULE eq h'01
		mov		#BSC_MCR_MEM_TYPE_SDRAM, r0	; based on val in init.src
	.aelse
		mov		#BSC_MCR_MEM_TYPE_EDO, r0	; based on val in init.src
	.aendi

	mov.l	r0, @r2

	.aif SDRAM_MODULE eq h'01
		mov.l	#h'FF940190, r1
		mov.b	r1, @r1
	.aendi

	mov		#BSC_PCR, r2					; Set PCMCIA control,
	mov		#BSC_PCR_WAIT_INSERTED, r0		; Same as default
	mov.w	r0, @r2

	mov		#BSC_RTCOR, r2					; Initialize maximum refresh count
	mov		#BSC_RTCOR_MAX_COUNT, r1
	mov.w	r1, @r2

	mov		#BSC_RTCNT, r2;					; Set refresh counter
	mov		#BSC_RTCNT_START, r1			; Start at 0
	mov.w	r1, @r2			

	mov		#BSC_RTCSR, r2					; Set refresh control
	mov		#BSC_RTCSR_SETTINGS, r1			; Refresh cycle CKIO/4
	mov.w	r1, @r2

	.aif	SDRAM_MODULE eq h'01
MCR_timer:
		mov.l	#h'0000fff0, r0

MCR_loop:
		add		#(-1), r0
		tst		r0, r0
		bf		MCR_loop

		mov		#BSC_MCR, r2
		mov		#BSC_MCR_SDRAM_MRSET, r0
		mov.l   r0, @r2						;265 12 bit cas
		mov.l	#h'FF940190, r1
		mov.b	r1, @r1
	.aendi

	; Disable the Cache, the kernel will take care of it.

	mov		#CCN_CCR, r1					; ptr to Cache control register
	mov		#CCN_CCR_DISABLE, r0	
	mov.l	r0, @r1							; disable the cache

	; Enable output of TCLK for HD64464
	mov.l	#TMU_TOCR,r1		;TCLK output for MediaQ ( MQ100 )
	mov		#1,r0				;
	mov.b	r0,@r1				;

	; Load the Kernel and JUMP

	mov		#KernelStart, r0				; load address of KernelStart 
	mov		#h'20000000, r2					; moves from section P1(cached) to P2 (uncached)
	or		r2, r0

	jmp		@r0								; execute KernelStart in P1 section
	nop
	.endf

;************************************************************************************
; SH4 RTC Alarm interrupt service routine
;
;	This routine is invoked when the real time matches the alarm time. Since the year
; is not included as part of the alarm time, the year must be checked and the interrupt
; will be ignored if the year doesn't match.
;
; Registers: r0-r3, r6 available for use
;
;      Entry   in register bank 1, exceptions blocked
;      Exit    (r0) = interrupt dispostion information
;                      (see nkintr.h for values)
;      Uses    r0-r3,r6
; Clear the alarm flag.

	LEAF_ENTRY _AlarmISR
	mov		#RTC_RCR1, r2					; (r0) = RTC control register 1 contents
	mov.b	@r2, r0
	mov		#~RTC_RCR1_AF, r1
	and		r1, r0
	mov.b	r0, @r2							; clear alarm flag in control register 1

; Compare the current year with the alarm year.

	mov		#_AlarmYear, r1					; (r1) = ptr to alarm year
	mov.w	@r1, r1							; (r1) = alarm year value
	mov		#RTC_RYRCNT, r3					; (r3) = ptr to RYRCNT (current year)
	mov.w	@r3, r2							; (r2) = current year (in BCD)
	cmp/eq	r1, r2
	bf/s	aisr40							; year matches, signal the alarm
	mov		#SYSINTR_NOP, r0

	mov		#RTC_RCR1, r2					; (r0) = RTC control register 1 contents
	mov.b	@r2, r0
	mov		#~(RTC_RCR1_AIE|RTC_RCR1_AF) , r1
	and		r1 , r0
	mov.b	r0, @r2							; Disable alarm interrupt in control register 1
	mov		#SYSINTR_RTC_ALARM, r0			; (r0) = interrupt cause

aisr40:
	rts
	nop
	.endf

;*****************************************************************************
;* OEMPowerOff - OFF button handler
;*
;* This routine is invoked when the OFF button is pressed. It is responsible
;* for any final power off state and putting the cpu into standby.
;*
;*	Entry	none
;*	Exit	none
;*	Uses	r0-r3
;*****************************************************************************
	LEAF_ENTRY _OEMPowerOff

	mov	#h'50000030, r0
	ldc	r0, SR
 
   	sleep
 
	mov	#h'400000f0, r0
	ldc	r0, SR
	rts
	WRITE_LEDS	H'0f
	nop
	.endf

;*****************************************************************************
;* OEMIdle - system idle
;*
;* This routine is called by the kernel when there are no threads ready to
;* run. The CPU should be put into a reduced power mode and halted. It is important
;* to be able to resume execution quickly upon receiving an interrupt.
;*
;* NOTE: Exceptions are blocked when this routine called and must not be reenabled
;* unless the functions is going to return immediately. The SH4 ignores the block bit
;* in the PSR when sleeping so it is not necessary to enable interrupts before issuing
;* the sleep instruction.
;*
;*	Entry	Exceptions blocked
;*	Exit	none
;*	Uses	r0-r3
;*****************************************************************************
	LEAF_ENTRY OEMIdle

	sleep
	rts
	nop
	.endf

;*****************************************************************************
;* OEMNMI - non-maskable interrupt handler
;*
;* This routine is called when a non-maskable interrupt occurs. It should return
;* an interrupt cause the same as other interrupt service routines.
;*
;* Registers: r0-r3,r6 available for use.
;*
;*     Entry   in register bank 1, exceptions blocked
;*     Exit    (r0) = interrupt dispostion information
;*                   (see nkintr.h for values)
;*     Uses    r0
;*****************************************************************************
	LEAF_ENTRY OEMNMI

	rts
	mov	#SYSINTR_NOP, r0
	.endf

	.end