initpci.c

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C语言 代码 · 共 228 行

/*

  Copyright(c) 1998,1999 SIC/Hitachi,Ltd.

	Module Name:

		initpci.c

	Revision History:

		26th April 1999		Released

*/

#include <windows.h>
#include <nkintr.h>

#include "shx.h"
#include "cc.h"
#include "platform.h"

/*****************************************************************************
*	FUNCTION :		InitPCI()
*****************************************************************************/
void InitPCI()
{
unsigned long pci_base_add0;
unsigned long pci_base_add1;
unsigned long pci_idsel_num;
unsigned long pci_wait;

#define DEBUG_PCI_AT_LOCAL      0
#define DEBUG_PCI_PRINT         0
#define DEBUG_PCI_VERS          0x0123
#define PCIBUS_DEV_VEN       *(volatile unsigned long*)  0xA4000000
#define PCIBUS_STAT_CMD      *(volatile unsigned long*)  0xA4000004
#define PCIBUS_CC_REV        *(volatile unsigned long*)  0xA4000008
#define PCIBUS_HDR_LATTIM    *(volatile unsigned long*)  0xA400000C
#define PCIBUS_BASE0         *(volatile unsigned long*)  0xA4000010
#define PCIBUS_BASE1         *(volatile unsigned long*)  0xA4000014
#define PCIBUS_BASE2         *(volatile unsigned long*)  0xA4000018
#define PCIBUS_BASE3         *(volatile unsigned long*)  0xA400001c
#define PCIBUS_BASE4         *(volatile unsigned long*)  0xA4000020
#define PCIBUS_BASE5         *(volatile unsigned long*)  0xA4000024
#define PCIBUS_EXROM_BASE    *(volatile unsigned long*)  0xA4000030
#define V292_PCI_DEV_VEN     *(volatile unsigned long*)  0xA5800000
#define V292_PCI_STAT_CMD    *(volatile unsigned long*)  0xA5800004
#define V292_PCI_CC_REV      *(volatile unsigned long*)  0xA5800008
#define V292_PCI_HDR_CFG     *(volatile unsigned long*)  0xA580000C
#define V292_PCI_IO_BASE     *(volatile unsigned long*)  0xA5800010
#define V292_PCI_BASE0       *(volatile unsigned long*)  0xA5800014
#define V292_PCI_BASE1       *(volatile unsigned long*)  0xA5800018
#define V292_PCI_SUB_VEND    *(volatile unsigned long*)  0xA580002C
#define V292_PCI_ROM         *(volatile unsigned long*)  0xA5800030
#define V292_PCI_BPARAM      *(volatile unsigned long*)  0xA580003C
#define V292_PCI_MAP0        *(volatile unsigned long*)  0xA5800040
#define V292_PCI_MAP1        *(volatile unsigned long*)  0xA5800044
#define V292_PCI_INT_STAT    *(volatile unsigned long*)  0xA5800048
#define V292_PCI_INT_CFG     *(volatile unsigned long*)  0xA580004C
#define V292_LB_BASE0        *(volatile unsigned long*)  0xA5800054
#define V292_LB_BASE1        *(volatile unsigned long*)  0xA5800058
#define V292_LB_MAP0_RES     *(volatile unsigned long*)  0xA580005C
#define V292_LB_MAP1_RES     *(volatile unsigned long*)  0xA5800060
#define V292_LB_IO_BASE_0    *(volatile unsigned long*)  0xA400006C
#define V292_LB_IO_BASE_RES  *(volatile unsigned long*)  0xA580006C
#define V292_FIFO_PRIOR_CFG  *(volatile unsigned long*)  0xA5800070
#define V292_LB_IM_IS_STAT   *(volatile unsigned long*)  0xA5800074
#define V292_LB_CFG_SYSTEM   *(volatile unsigned long*)  0xA5800078
#define FPGA_CSR             *(volatile unsigned long*)  0xA6000000
#define FPGA_PCI_CNT         *(volatile unsigned short*) 0xA6000004

	NKDbgPrintfW(L">>>>>>>>>>> Initialize PCI...v.001_%04x>>>>>>>>\r\n",DEBUG_PCI_VERS);
	FPGA_PCI_CNT = 0x00FF;

#if DEBUG_PCI_PRINT
	OEMWriteDebugString(TEXT(">>>>>>>>>>> Reset PCI&BUS >>>>>>>>>>>>>>>\r\n"));
#endif
	
	pci_wait = 0x00400000;
	while ( --pci_wait )
	{
		FPGA_CSR;
	}
	FPGA_PCI_CNT = 0x80FF;
#if 1
	pci_wait = 0x00200000;
	while ( --pci_wait )
	{
		FPGA_CSR;
	}
#endif
	
	V292_LB_IO_BASE_0		= 0x01800000;
	V292_LB_CFG_SYSTEM		= 0x00008077;

#if 1
	pci_wait = 0x00003000;
	while ( --pci_wait )
	{
		FPGA_CSR;
	}
#endif
	V292_LB_CFG_SYSTEM		= 0x03c08000;
	V292_PCI_STAT_CMD		= 0x00000246;
	V292_PCI_HDR_CFG		= 0x00000800;
	V292_LB_BASE0			= 0x00000041;
	V292_LB_BASE1			= 0x04000001;
	V292_LB_MAP0_RES		= 0x00060000;
	V292_LB_MAP1_RES		= 0x01020000;
	V292_FIFO_PRIOR_CFG		= 0x000f0000;
	V292_PCI_IO_BASE		= 0xFFFF0000;
	V292_PCI_BASE0			= 0x60000000;
	V292_PCI_BASE1			= 0x60100000;
	V292_PCI_MAP0			= 0xa8c00000;
	V292_PCI_MAP1			= 0xa8d00000;
	/* PCI BUS init  */
	pci_base_add0			= 0x00000000;
	pci_base_add1			= 0x04000000;
	V292_LB_MAP0_RES		= 0x000a0000;

#if 1
	pci_wait = 0x00000030;
	while ( --pci_wait )
	{
		FPGA_CSR;
	}
#endif

	for(pci_idsel_num = 0;pci_idsel_num <3;pci_idsel_num++)
	{
		if( pci_idsel_num == 0 )
			FPGA_PCI_CNT = 0x90FF;				/* idsel0:9   idsel1:a   idsel0:c  */
		else if( pci_idsel_num == 1 )
			FPGA_PCI_CNT = 0xa0FF;				/* idsel0:9   idsel1:a   idsel0:c  */
		else if( pci_idsel_num == 2 )
			FPGA_PCI_CNT = 0xc0FF;				/* idsel0:9   idsel1:a   idsel0:c  */
		else
			FPGA_PCI_CNT = 0x80FF;				/* idsel0:9   idsel1:a   idsel0:c  */

#if DEBUG_PCI_PRINT
		NKDbgPrintfW(L">>>>>>>>>>> Card_No.%d check >>>>>>>>>>>\r\n", pci_idsel_num);
		NKDbgPrintfW(L"PCIBUS_DEV_VEN       = %08x\r\n", PCIBUS_DEV_VEN);
#endif
#if 1
		pci_wait = 0x00000030;
		while ( --pci_wait )
		{
			FPGA_CSR;
		}
#endif
		if (PCIBUS_DEV_VEN != 0xFFFFFFFF ) 
		{
			PCIBUS_STAT_CMD	= 0x00000003;
			PCIBUS_BASE0	= 0xFFFFFFFF;
			PCIBUS_BASE1	= 0xFFFFFFFF;
			PCIBUS_BASE2	= 0xFFFFFFFF;
			PCIBUS_BASE3	= 0xFFFFFFFF;
			PCIBUS_BASE4	= 0xFFFFFFFF;
			PCIBUS_BASE5	= 0xFFFFFFFF;
#if 1
			pci_wait = 0x00000030;
			while ( --pci_wait )
			{
				FPGA_CSR;
			}
#endif

#if DEBUG_PCI_PRINT
			NKDbgPrintfW(L"PCIBUS_BASE0(R)      = %08x\r\n", PCIBUS_BASE0);
			NKDbgPrintfW(L"PCIBUS_BASE1(R)      = %08x\r\n", PCIBUS_BASE1);
#endif

			if((PCIBUS_BASE0 & 0x00000001) == 0x00000000)
			{
				if((PCIBUS_BASE0 & 0xFFFFFFF0)  != 0x00000000)
				{
					PCIBUS_BASE0 = pci_base_add0;
					pci_base_add0 += 0x01000000;
				}
			}
			else
			{
				if((PCIBUS_BASE0 & 0xFFFFFFF0)  != 0x00000000)
				{
					PCIBUS_BASE0 = pci_base_add1;
					pci_base_add1 += 0x00010000;
				}
			}
			if(PCIBUS_BASE1 & 0x00000001 == 0x00000000)
			{
				if((PCIBUS_BASE1 & 0xFFFFFFF0)  != 0x00000000)
				{
					PCIBUS_BASE1 = pci_base_add0;
					pci_base_add0 += 0x01000000;
				}
			}
			else
			{
				if((PCIBUS_BASE1 & 0xFFFFFFF0)  != 0x00000000)
				{
					PCIBUS_BASE1 = pci_base_add1;
					pci_base_add1 += 0x00010000;
				}
			}
			PCIBUS_STAT_CMD = 0x00000003;

#if DEBUG_PCI_PRINT
			NKDbgPrintfW(L"FPGA_PCI_CNT         = %08x\r\n", FPGA_PCI_CNT);
			NKDbgPrintfW(L"PCIBUS_DEV_VEN       = %08x\r\n", PCIBUS_DEV_VEN);
			NKDbgPrintfW(L"PCIBUS_STAT_CMD      = %08x\r\n", PCIBUS_STAT_CMD);
			NKDbgPrintfW(L"PCIBUS_CC_REV        = %08x\r\n", PCIBUS_CC_REV);
			NKDbgPrintfW(L"PCIBUS_HDR_LATTIM    = %08x\r\n", PCIBUS_HDR_LATTIM);
			NKDbgPrintfW(L"PCIBUS_BASE0         = %08x\r\n", PCIBUS_BASE0);
			NKDbgPrintfW(L"PCIBUS_BASE1         = %08x\r\n", PCIBUS_BASE1);
			NKDbgPrintfW(L"PCIBUS_BASE2         = %08x\r\n", PCIBUS_BASE2);
			NKDbgPrintfW(L"PCIBUS_BASE3         = %08x\r\n", PCIBUS_BASE3);
			NKDbgPrintfW(L"PCIBUS_BASE4         = %08x\r\n", PCIBUS_BASE4);
			NKDbgPrintfW(L"PCIBUS_BASE5         = %08x\r\n", PCIBUS_BASE5);
			NKDbgPrintfW(L"pci_base_add0(MEM)   = %08x\r\n", pci_base_add0);
			NKDbgPrintfW(L"pci_base_add1(I/O)   = %08x\r\n", pci_base_add1);
#endif
		}
	}
	FPGA_PCI_CNT = 0xF0FF;/* idsel0:9   idsel1:a   idsel0:c  */
	V292_LB_MAP0_RES = 0x00060000;
	OEMWriteDebugString(TEXT(">>>>>>>>>>> Initialize PCI...end       >>>>>>>>\r\n"));
}