boot.inc

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· INC 代码 · 共 114 行

;
;  Copyright(c) 1998,1999 SIC/Hitachi,Ltd.
;
;	Module Name:
;
;		boot.inc
;
;	Revision History:
;
;		26th April 1999		Released
;		14th June  1999		Changed initial value of CPG_FRQCR.([I:B:P]=[6:2:1]-->[6:1:1])
;		6th  July  1999		Changed initial value of CPG_FRQCR.([I:B:P]=[6:1:1]-->[6:3/2:3/2])
;		8th  July  1999		Changed Changed bus width of AREA4
;

; This macro simpy takes a value and writes it to the LED display.  Currently,
; it needs to be modified to adjust for the different methodology of writing 
; to the LEDs


;; NKCH: For ASPEN WRITE_LEDS does not do anything at present.
	.macro	WRITE_LEDS	Value	; for 1284
	;; mov.b	#\Value,r9			; Pattern to display
	;; mov.b	r9,@r8				; Write the LEDs
	.endm

; Clock Pulse Generator (CPG)

ZERO_TME						.equ	CPG_WTCSR_COOKIE	| h'00
SET_CKS							.equ	CPG_WTCSR_COOKIE	| CPG_WTCSR_CKS_1024
COUNT_INIT						.equ	CPG_WTCNT_COOKIE	| h'00

CPG_FRQCR_CLOCK					.equ	CPG_FRQCR_CKOEN		| CPG_FRQCR_PLL1EN	| 
+										CPG_FRQCR_PLL2EN	| CPG_FRQCR_IFC_1	| 
+										CPG_FRQCR_BFC_4		| CPG_FRQCR_PFC_4

BSC_BCR1_MEMORY_MAP_EDO			.equ	BSC_BCR1_DRAM_A2N3D	| BSC_BCR1_A56PCM               
BSC_BCR1_MEMORY_MAP_SDRAM		.equ	BSC_BCR1_DRAM_A2N3S | BSC_BCR1_A56PCM               

BSC_BCR2_A1_BUS_WIDTH			.equ	BSC_BCR2_A1SZ_32
BSC_BCR2_A2_BUS_WIDTH			.equ	BSC_BCR2_A2SZ_32
BSC_BCR2_A3_BUS_WIDTH			.equ	BSC_BCR2_A3SZ_64

	.aif ENABLE_HD64463_DY eq h'01
BSC_BCR2_A4_BUS_WIDTH			.equ	BSC_BCR2_A4SZ_16
	.aelse
BSC_BCR2_A4_BUS_WIDTH			.equ	BSC_BCR2_A4SZ_32
	.aendi

BSC_BCR2_A5_BUS_WIDTH			.equ	BSC_BCR2_A5SZ_8
BSC_BCR2_A6_BUS_WIDTH			.equ	BSC_BCR2_A6SZ_8

BSC_BCR2_BUS_WIDTHS				.equ	BSC_BCR2_A1_BUS_WIDTH	|
+										BSC_BCR2_A2_BUS_WIDTH	|
+										BSC_BCR2_A3_BUS_WIDTH	| 
+										BSC_BCR2_A4_BUS_WIDTH	|
+										BSC_BCR2_A5_BUS_WIDTH	|
+										BSC_BCR2_A6_BUS_WIDTH


BSC_WCR1_IDLE_STATES			.equ	BSC_WCR1_A6IW_3		|
+										BSC_WCR1_A5IW_3		|
+										BSC_WCR1_A4IW_3		|
+										BSC_WCR1_A3IW_3		|
+										BSC_WCR1_A2IW_3		|
+										BSC_WCR1_A1IW_3		|
+										BSC_WCR1_A0IW_3		|
+										BSC_WCR1_DMAIW_3

BSC_WCR2_WAIT_STATES			.equ	BSC_WCR2_A6W_15		| BSC_WCR2_A6B_7	|
+										BSC_WCR2_A5W_15		| BSC_WCR2_A5B_7	|
+										BSC_WCR2_A4W_3		|
+										BSC_WCR2_A3W_DRAM_4	|
+										BSC_WCR2_A2W_NORMAL_3	|
+										BSC_WCR2_A1W_15		|
+										BSC_WCR2_A0W_12		| BSC_WCR2_A0B_3

BSC_WCR3_WAIT_INSERTED			.equ	BSC_WCR3_A6S_0	| BSC_WCR3_A6H_0	|
+										BSC_WCR3_A5S_0	| BSC_WCR3_A5H_0	|
+										BSC_WCR3_A4S_1	| BSC_WCR3_A4H_0	|
+										BSC_WCR3_A3S_0	| BSC_WCR3_A3H_0	|
+										BSC_WCR3_A2S_0	| BSC_WCR3_A2H_0	|
+										BSC_WCR3_A1S_0	| BSC_WCR3_A1H_0	|
+										BSC_WCR3_A0S_0	| BSC_WCR3_A0H_0

BSC_MCR_MEM_TYPE_EDO			.equ	BSC_MCR_RASD	| BSC_MCR_TPC_1		|
+										BSC_MCR_TRWL_2	| BSC_MCR_BE		|
+										BSC_MCR_AMX_11	| BSC_MCR_RFSH		|
+										BSC_MCR_EDOMODE

BSC_MCR_MEM_TYPE_SDRAM			.equ	BSC_MCR_TRC_9	| BSC_MCR_RCD_4		|
+										BSC_MCR_TRWL_4	| BSC_MCR_AMX_11	|
+										BSC_MCR_RFSH

BSC_MCR_SDRAM_MRSET				.equ	BSC_MCR_MRSET	| BSC_MCR_MEM_TYPE_SDRAM 

BSC_PCR_WAIT_INSERTED			.equ	BSC_PCR_A5PCW_0	| BSC_PCR_A6PCW_0	|
+										BSC_PCR_A5TED_6	| BSC_PCR_A6TED_6	|
+										BSC_PCR_A5TEH_2	| BSC_PCR_A6TEH_2

BSC_RTCSR_SETTINGS				.equ	BSC_RTCSR_COOKIE	|
+										BSC_RTCSR_CKS_4		|
+										BSC_RTCSR_LMTS

BSC_RTCNT_START					.equ	BSC_RTCNT_COOKIE	| 0  

BSC_RTCOR_MAX_COUNT				.equ	BSC_RTCOR_COOKIE	| h'10

; Cache Control Register

CCN_CCR_MODE					.equ	CCN_CCR_WT
CCN_CCR_DISABLE					.equ	0x00