bigsur.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 332 行
H
332 行
/******************************************************************************
* File: bigsur.h
* Author: Naresh Gupta (nkgupta@hotmail.com)
* Date: Thursday Sept 30, 1999
* Organization: Hitachi Semiconductor America Inc.
* Purpose: Will contain all definitions specific to bigsur
*
* Copyright (C) 1999 Hitachi Semiconductor America Inc.
******************************************************************************/
/******************************************************************************
* Important Note:-
* ===============
*
* To properly view this file, you need to set tabstop=4 in your editor
*****************************************************************************/
#ifndef _BIGSUR_H
#define _BIGSUR_H
/******************************************************************************
* User modifiable stuff
*****************************************************************************/
/*
* Define DISABLE_PPSH if you do not want ppsh in the image. This is useful
* to speed up booting time when ppsh is not present.
*/
#define DISABLE_PPSH
/******************************************************************************
* End of User modifiable stuff
*****************************************************************************/
/******************************************************************************
* Peripheral Base Addresses for bigsur.
*****************************************************************************/
#define FPGA_BASE 0xB0000000
// FPGA...
#define ALPHA_LED (FPGA_BASE + 0x01FFFE00 + 0xE0) // Alphanumeric LEDS, 0xE0 is the character RAM display offset.
#define LED_ALPHA ALPHA_LED // Same as above
#define PAR_BASE (FPGA_BASE + 0x01FFF600) // Parallel Port
#define PILOT_LED_ADDR (FPGA_BASE + 0x01FFFC00) // Pilot LEDs
/* TBD */
// #define FPGA_CMD_ADDR 0xA4040000 // FPGA Command Register
/* TBD */
#define ATAPI_BASE (FPGA_BASE + 0x01FDF000) // IDE
// Companion Chips...
#define HD64465_BASE FPGA_BASE // HD64465
#define HD64464_BASE FPGA_BASE // HD64464 if present.
#define SMC_BASE (FPGA_BASE + 0x01FE0000) // Base of SMC91C100FD Ethernet
#define ETHERNET_BASE SMC_BASE
// PCI...
#define PHYSICAL_PCI_MEM_BASE 0xA8000000 // Base for Memory accesses
#define PHYSICAL_PCI_CONFIG_BASE 0xA8000000 // Configuration access
#define PHYSICAL_PCI_IO_BASE 0xA4000000 // I/O Access
#define PHYSICAL_V3_INTERNAL_REG_BASE (FPGA_BASE + 0x01000000) // Internal registers of V3
// RAM/Flash...
#define DRAM_BASE 0x8C000000 // RAM
#define DRV_GLOBAL_OFFSET 0x00150000 // Driver Globals
#define DRV_GLOBAL_BASE (DRAM_BASE + DRV_GLOBAL_OFFSET)
/******************************************************************************
* ATAPI related definitions.
*****************************************************************************/
#define ATAPI_SIZE 0xFFFF
// Temporary buffer for ATAPI
#define ATAPI_WORKBASE (DRV_GLOBAL_BASE + 0x1000)
#define ATAPI_WORKSIZE 0x020000
// ATAPI registers
// TBD: Write full names of these registes in comments.
#define ATAPI_REG_DATW_OFFSET 0x0D00
#define ATAPI_REG_AERR_OFFSET 0x0D04
#define ATAPI_REG_FETR_OFFSET 0x0D04
#define ATAPI_REG_IRRN_OFFSET 0x0D08
#define ATAPI_REG_RSVE_OFFSET 0x0D0c
#define ATAPI_REG_BCTL_OFFSET 0x0D10
#define ATAPI_REG_BCTH_OFFSET 0x0D14
#define ATAPI_REG_DSEL_OFFSET 0x0D18
#define ATAPI_REG_STAT_OFFSET 0x0D1c
#define ATAPI_REG_COMD_OFFSET 0x0D1c
#define ATAPI_REG_ASTA_OFFSET 0x0E18
#define ATAPI_REG_DCTR_OFFSET 0x0E18
/*****************************************************************************
* FPGA Interrupt Mask and Status Register
*****************************************************************************/
/*
* Please note that the Interrupt Mask register is actually an Interrupt
* UnMask Register. Whatever bits are made 1, the corresponding interrupts
* are allowed to occur
*/
#define INT_STAT0 (FPGA_BASE + 0x01FDFA00)
#define INT_STAT1 (FPGA_BASE + 0x01FDF900)
#define INT_STAT2 (FPGA_BASE + 0x01FDF800)
#define INT_STAT3 (FPGA_BASE + 0x01FDF700)
#define INT_IMASK0 (FPGA_BASE + 0x01FDF600)
#define INT_IMASK1 (FPGA_BASE + 0x01FDF500)
#define INT_IMASK2 (FPGA_BASE + 0x01FDF400)
#define INT_IMASK3 (FPGA_BASE + 0x01FDF300)
/* No need to define ISTAT separately since the bit positions are the
* same as the imask register.
*/
/* Interrupt Mask Register 0 */
#define FPGA_IMASK_AUTOINT 0x01 // Auto PC interrupt
/* Interrupt Mask Register 1 */
#define FPGA_IMASK_B4_INT 0x01 // B4_Int interrupt
#define FPGA_IMASK_SH7751_INTA 0x02 // Sh7751 IntA interrupt
#define FPGA_IMASK_A_INTA 0x04 // A_INTA interrupt
#define FPGA_IMASK_A_INTB 0x08 // A_INTB interrupt
#define FPGA_IMASK_A_INTC 0x10 // A_INTC interrupt
#define FPGA_IMASK_A_INTD 0x20 // A_INTD interrupt
#define FPGA_IMASK_IDE_INT 0x40 // IDE interrupt
#define FPGA_IMASK_DBG_INT 0x80 // DBG interrupt
/* Interrupt Mask Register 2 */
#define FPGA_IMASK_INTP 0x01 // INTP interrupt
#define FPGA_IMASK_INTS 0x02 // INTS interrupt
#define FPGA_IMASK_INTA 0x04 // INTA interrupt
#define FPGA_IMASK_INTB 0x08 // INTB interrupt
#define FPGA_IMASK_INTC 0x10 // INTC interrupt
#define FPGA_IMASK_INTD 0x20 // INTD interrupt
#define FPGA_IMASK_DEG 0x40 // DEG interrupt
#define FPGA_IMASK_ENUM 0x80 // ENUM interrupt
/* Interrupt Mask Register 3 */
#define FPGA_IMASK_USC_INT 0x01 // Mask interrupt form CPCI controller
#define FPGA_IMASK_U465 0x02 // HD64465 interrupt
#define FPGA_IMASK_U464 0x04 // HD64464 interrupt
#define FPGA_IMASK_ENETINT 0x08 // Ethernet interrupt
#ifdef JUNK
/***************************General *****************************************/
#define VL(x) (*(volatile long *)(x))
/***************************LED *********************************************/
#define LED VL(PILOT_LED_ADDR )
#endif JUNK
/******************************************************************************
* Flash related stuff
*****************************************************************************/
typedef unsigned long flash_t;
#define FLASH_BANK_SIZE (1024 * 1024 * 16)
#define FLASH_BANK_COUNT 2
#define FLASH_SIZE (FLASH_BANK_SIZE * FLASH_BANK_COUNT)
#define SECTOR_SIZE (0x20000L*2) // 128k sectors per I.C.,
// 2 I.C.'s on bus
#define LAST_SECTOR ((FLASH_SIZE/SECTOR_SIZE)-1)
#define FLASH_START 0xa8000000
#define FLASH_END (FLASH_START+FLASH_SIZE)
#define FLASH_BLOCK_SIZE SECTOR_SIZE
#define FLASH_BLOCK_QTY (LAST_SECTOR+1)
#define SECTOR_SHIFT 18 // Bits to shift to get Sector number
#define FLASH_WIDTH (sizeof(flash_t) << 3)
#define FLASH_ADDRESS ((flash_t *)0xa8000000)
#define ROM_ADDRESS (flash_t *)0xA0000000
#define ALL_FLASH -1
#define FLASH_READY 0x00800080
#define FL_ADDRESS_ERROR 1
/* Constants */
enum
{
FLASH_SUCCESS,
FLASH_BUSY,
FLASH_ERROR,
FLASH_TIMEOUT,
FLASH_ILLEGAL_SECTOR
};
/* Flash related addresses for bigsur */
/* bigsur has 32 Mb of Flash */
#define FLASH_ADDR_START 0x80000000
#define FLASH_ADDR_END 0x82000000
extern unsigned ulRamBufStart;
// Since we have 32 Mb of Flash currently, it's sufficient to have a
// 32 Mb buffer for Flash data.
#define FLASH_CACHE 0x8D000000
/******************************************************************************
* Start address of each AREA
*****************************************************************************/
#define AREA_0 0x00000000
#define AREA_1 0x04000000
#define AREA_2 0x08000000
#define AREA_3 0x0C000000
#define AREA_4 0x10000000
#define AREA_5 0x14000000
#define AREA_6 0x18000000
#define AREA_7 0x1C000000
/*****************************************************************************
* Switch SW1
****************************************************************************/
#define BIGSUR_SW1 (FPGA_BASE + 0x01FFFB00)
#define BIGSUR_SW2 (FPGA_BASE + 0x01FFF900) // upper 4 bits of this register.
#define BIGSUR_SW1_BOOT_PROM 0x01
#define BIGSUR_SW1_MISCSW_N 0x02
#define BIGSUR_SW1_DEBUG_SER_N 0x04
#define BIGSUR_SW1_FLWREN 0x08
#define BIGSUR_SW1_FLASH_PROT_N 0x10
#define BIGSUR_SW1_SYSRESET0 0x20
#define BIGSUR_SW1_SYSRESET1 0x40
#define BIGSUR_SW1_SYSRESET2 0x80
// Right now the bits are flipped (1-4 is actually 4-1, and complimented,
// 1 is 0 and 0 is 1. Put a software patch meanwhile
#define BIGSUR_SW2_LM_ETHERNET 0x0C // Load Monitor thru Ethernet.
#define BIGSUR_SW2_LM_SERIAL 0x04 // Load Monitor thru Serial.
#define BIGSUR_SW2_LM_PARALLEL 0x08 // Load Monitor thru Parallel.
/******************************************************************************
* Parallel Port
*****************************************************************************/
#define PAR_CONTROL2_REG 0xB1FFF600 // (PAR_BASE)
#define PAR_CONTROL1_REG 0xB1FFF700 // (PAR_BASE+ 0x100)
#define PAR_DATA_REG 0xB1FDFF00 // (PAR_BASE+ 0x900)
/**********************************************************************
FPGA DMA Registers
**********************************************************************/
#define FPGA_DMA_REG0 0xB1FDFC00
#define FPGA_DMA_REG1 0xB1FDFB00
#define FPGA_DMA_REG0_64465CH0 0x2
#define FPGA_DMA_REG0_64465CH1 0x4
/******************************************************************************
* PCMCIA definitions
*****************************************************************************/
#define PCMCIA0_ATTR_WIN_BASE (AREA_6 + 0x00000000)
#define PCMCIA1_ATTR_WIN_BASE (AREA_5 + 0x00000000)
#define PCMCIA_ATTR_WIN_SIZE 0x01000000 // 16 MB
#define PCMCIA0_CMN_WIN_BASE (AREA_6 + 0x01000000)
#define PCMCIA1_CMN_WIN_BASE (AREA_5 + 0x01000000)
#define PCMCIA_CMN_WIN_SIZE 0x01000000 // 16 MB
#define PCMCIA0_IO_WIN_BASE (AREA_6 + 0x02000000)
#define PCMCIA1_IO_WIN_BASE (AREA_5 + 0x02000000)
#define PCMCIA_IO_WIN_SIZE 0x01000000 // 16 MB
#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x1000000 // Only 16 Mbyte mapped in system address space
#define PCMCIA_NUM_WINDOWS 6
// This needs to be moved to cached memory maybe later.
#define PhysicaVmemAddr (HD64464_BASE + 0x02000000)
#define CURSOR_BASE (HD64464_BASE + 0x020F0000)
/******************************************************************************
* Timing related constants.
*****************************************************************************/
#if 0 // Will investigate these values later - Naresh
#define FREQ_MULTIPLIER_FACTOR 0x5
#define SYSTEM_CLOCK_FREQ (333333 * FREQ_MULTIPLIER_FACTOR)
#define USEC_TO_CLOCK_LOW (0x15555555 * FREQ_MULTIPLIER_FACTOR)
#define USEC_TO_CLOCK_HIGH (0x00000002 * FREQ_MULTIPLIER_FACTOR)
#define CLOCK_TO_USEC_LOW (0x7AE147AE / FREQ_MULTIPLIER_FACTOR)
#define CLOCK_TO_USEC_HIGH (0x00000000 / FREQ_MULTIPLIER_FACTOR)
#else // 0
#define SYSTEM_CLOCK_FREQ 50000000
#define USEC_TO_CLOCK_LOW 0x80000000
#define USEC_TO_CLOCK_HIGH 0x0000000C
#define CLOCK_TO_USEC_LOW 0x147AE148
#define CLOCK_TO_USEC_HIGH 0x00000000
#endif // 0
// Set interrupt priority
#define INTC_IPRA_TMU0_INT 0x1000
#define INTC_IPRA_TMU1_INT 0x0E00
#define INTC_IPRA_TMU2_INT 0x00F0
#define INTC_IPRA_RTC_INT 0x000F
#define INTC_IPRB_WDT_INT 0x0000
#define INTC_IPRB_REF_INT 0x0000
#define INTC_IPRB_SCI_INT 0x0000
#define INTC_IPRC_DMAC_INT 0x0A00
#define INTC_IPRC_SCIF_INT 0x00B0
#define INTC_IPRC_JTAG_INT 0x0000
/* Dummy values, till i start working on interrupts. */
#define SYSINTR_PCI_SLOT0 1
#define SYSINTR_PCI_SLOT1 1
#define SYSINTR_PCI_SLOT2 1
#endif _BIGSUR_H
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