cchal.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 587 行 · 第 1/2 页

#define TMI_ON				   0x01			/* #S1_FIR TMI bit in IIRC3R On */
#define TMI_OFF				   0xFE			/* #S1_FIR TMI bit in IIRC3R Off */
#define RTS_ON				   0x80			/* #S1_FIR RTS bit in IIRC3R Off */
#define ERDVI_ON			   0x01			/* #S1_FIR ERDVI bit in IRIER On */
#define ERDVI_OFF			   0xFE			/* #S1_FIR ERDVI bit in IRIER Off */
#define ETHREI_ON			   0x02			/* #S1_FIR ETHREI bit in IRIER On */
#define ETHREI_OFF			   0xFD			/* #S1_FIR ETHREI bit in IRIER Off */
#define EMSI_ON				   0x08			/* #S1_FIR EMSI bit in IRIER On */
#define EMSI_OFF			   0xF7			/* #S1_FIR EMSI bit in IRIER Off */


/* End of Additions -- Naresh Gupta
 */

/* Eight bit registers - FIR and UART compatible
 * these names are compatible with the original 16550 driver
 * however, they are all on word boundaries
 */
#define RX_BUF_REG_OFFSET       0x0000		/* Receive Buffer Register */
#define INT_ENABLE_REG_OFFSET   0x0001		/* Interrupt Enable Register */
#define INT_ID_REG_OFFSET       0x0002		/* Interrupt ID Register */
#define LINE_CTRL_REG_OFFSET    0x0003		/* Line Control Register */
#define MODEM_CTRL_REG_OFFSET   0x0004		/* Modem Control Register */
#define LINE_STATUS_REG_OFFSET  0x0005		/* Line Status Register */
#define MODEM_STATUS_REG_OFFSET 0x0006		/* Modem Status Register */
#define SCRATCH_REG_OFFSET      0x0007		/* Scratch Register */

#define CC_16550_REG_STRIDE		2			/* each register is spaced 2 bytes apart */

#define UART_REGSIZE            0x10

/*----------------------------------------------------------------------------
 * PCMCIA
 * The PCMCIA also needs to share a few defines with the HAL, so they are listed 
 * here.
 */
/* Card Status Change (PCC0CSCR) Reg */
#define PCMCIA_SCR_GEN_CD_INT		0x80	/* Generate a CD interrupt */
#define PCMCIA_SCR_IREQ_INT_REQ		0x20	/* IREQ Int has occurred */
#define PCMCIA_SCR_STSCH_INT_REQ	0x10	/* STSCH Int has occurred */
#define PCMCIA_SCR_CD_INT_REQ		0x08	/* CD Int occurred */
#define PCMCIA_SCR_RDY_INT_REQ		0x04	/* RDY Int occurred */
#define PCMCIA_SCR_BW_INT_REQ		0x02	/* Batt warning int occurred */
#define PCMCIA_SCR_BE_INT_REQ		0x01	/* Batt dead int occurred */



/*----------------------------------------------------------------------------/
/* Port control module */

#define CC_PORT_REGBASE			(SYSTEM_ASIC_REGS_BASE+ASIC_PORT_OFFSET)
#define CC_PORT_REGSIZE			0x0050

#define CC_GPACR_OFFSET			0x0000
#define CC_GPBCR_OFFSET			0x0002
#define CC_GPCCR_OFFSET			0x0004
#define CC_GPDCR_OFFSET			0x0006
#define CC_GPECR_OFFSET			0x0008			// **tjn

#define CC_GPADR_OFFSET			0x0010
#define CC_GPBDR_OFFSET			0x0012
#define CC_GPCDR_OFFSET			0x0014
#define CC_GPDDR_OFFSET			0x0016
#define CC_GPEDR_OFFSET			0x0018			// **tjn

#define CC_GPAICR_OFFSET		0x0020
#define CC_GPBICR_OFFSET		0x0022
#define CC_GPCICR_OFFSET		0x0024
#define CC_GPDICR_OFFSET		0x0026
#define CC_GPEICR_OFFSET		0x0028

#define CC_GPAISR_OFFSET		0x0040
#define CC_GPBISR_OFFSET		0x0042
#define CC_GPCISR_OFFSET		0x0044
#define CC_GPDISR_OFFSET		0x0046
#define CC_GPEISR_OFFSET		0x0048

/****** Value of GPACR ******/
#define CC_PA7_MASK			0x3FFF
#define CC_PA7_FUNC_OUTPUT		0x0000
#define CC_PA7_OUTPUT			0x4000
#define CC_PA7_CMOS_ON_INPUT		0x8000
#define CC_PA7_CMOS_OFF_INPUT		0xC000

#define CC_PA6_MASK			0xCFFF
#define CC_PA6_FUNC_OUTPUT		0x0000
#define CC_PA6_OUTPUT			0x1000
#define CC_PA6_CMOS_ON_INPUT		0x2000
#define CC_PA6_CMOS_OFF_INPUT		0x3000

#define CC_PA5_MASK			0xF3FF
#define CC_PA5_FUNC_OUTPUT		0x0000
#define CC_PA5_OUTPUT			0x0400
#define CC_PA5_CMOS_ON_INPUT		0x0800
#define CC_PA5_CMOS_OFF_INPUT		0x0C00

#define CC_PA4_MASK			0xFCFF
#define CC_PA4_FUNC_OUTPUT		0x0000
#define CC_PA4_OUTPUT			0x0100
#define CC_PA4_CMOS_ON_INPUT		0x0200
#define CC_PA4_CMOS_OFF_INPUT		0x0300

#define CC_PA3_MASK			0xFF3F
#define CC_PA3_FUNC_OUTPUT		0x0000
#define CC_PA3_OUTPUT			0x0040
#define CC_PA3_CMOS_ON_INPUT		0x0080
#define CC_PA3_CMOS_OFF_INPUT		0x00C0

#define CC_PA2_MASK			0xFFCF
#define CC_PA2_FUNC_OUTPUT		0x0000
#define CC_PA2_OUTPUT			0x0010
#define CC_PA2_CMOS_ON_INPUT		0x0020
#define CC_PA2_CMOS_OFF_INPUT		0x0030

#define CC_PA1_MASK			0xFFF3
#define CC_PA1_FUNC_OUTPUT		0x0000
#define CC_PA1_OUTPUT			0x0004
#define CC_PA1_CMOS_ON_INPUT		0x0008
#define CC_PA1_CMOS_OFF_INPUT		0x000C

#define CC_PA0_MASK			0xFFFC
#define CC_PA0_FUNC_OUTPUT		0x0000
#define CC_PA0_OUTPUT			0x0001
#define CC_PA0_CMOS_ON_INPUT		0x0002
#define CC_PA0_CMOS_OFF_INPUT		0x0003

/****** Value of GPBCR ******/
#define CC_PB7_MASK			0x3FFF
#define CC_PB7_FUNC_OUTPUT		0x0000
#define CC_PB7_OUTPUT			0x4000
#define CC_PB7_CMOS_ON_INPUT		0x8000
#define CC_PB7_CMOS_OFF_INPUT		0xC000

#define CC_PB6_MASK			0xCFFF
#define CC_PB6_FUNC_OUTPUT		0x0000
#define CC_PB6_OUTPUT			0x1000
#define CC_PB6_CMOS_ON_INPUT		0x2000
#define CC_PB6_CMOS_OFF_INPUT		0x3000

#define CC_PB5_MASK			0xF3FF
#define CC_PB5_FUNC_OUTPUT		0x0000
#define CC_PB5_OUTPUT			0x0400
#define CC_PB5_CMOS_ON_INPUT		0x0800
#define CC_PB5_CMOS_OFF_INPUT		0x0C00

#define CC_PB4_MASK			0xFCFF
#define CC_PB4_FUNC_OUTPUT		0x0000
#define CC_PB4_OUTPUT			0x0100
#define CC_PB4_CMOS_ON_INPUT		0x0200
#define CC_PB4_CMOS_OFF_INPUT		0x0300

#define CC_PB3_MASK			0xFF3F
#define CC_PB3_FUNC_OUTPUT		0x0000
#define CC_PB3_OUTPUT			0x0040
#define CC_PB3_CMOS_ON_INPUT		0x0080
#define CC_PB3_CMOS_OFF_INPUT		0x00C0

#define CC_PB2_MASK			0xFFCF
#define CC_PB2_FUNC_OUTPUT		0x0000
#define CC_PB2_OUTPUT			0x0010
#define CC_PB2_CMOS_ON_INPUT		0x0020
#define CC_PB2_CMOS_OFF_INPUT		0x0030

#define CC_PB1_MASK			0xFFF3
#define CC_PB1_FUNC_OUTPUT		0x0000
#define CC_PB1_OUTPUT			0x0004
#define CC_PB1_CMOS_ON_INPUT		0x0008
#define CC_PB1_CMOS_OFF_INPUT		0x000C

#define CC_PB0_MASK			0xFFFC
#define CC_PB0_FUNC_OUTPUT		0x0000
#define CC_PB0_OUTPUT			0x0001
#define CC_PB0_CMOS_ON_INPUT		0x0002
#define CC_PB0_CMOS_OFF_INPUT		0x0003

/****** Value of GPCCR ******/
#define CC_PC7_MASK			0x3FFF
#define CC_PC7_FUNC_OUTPUT		0x0000
#define CC_PC7_OUTPUT			0x4000
#define CC_PC7_CMOS_ON_INPUT		0x8000
#define CC_PC7_CMOS_OFF_INPUT		0xC000

#define CC_PC6_MASK			0xCFFF
#define CC_PC6_FUNC_OUTPUT		0x0000
#define CC_PC6_OUTPUT			0x1000
#define CC_PC6_CMOS_ON_INPUT		0x2000
#define CC_PC6_CMOS_OFF_INPUT		0x3000

#define CC_PC5_MASK			0xF3FF
#define CC_PC5_FUNC_OUTPUT		0x0000
#define CC_PC5_OUTPUT			0x0400
#define CC_PC5_CMOS_ON_INPUT		0x0800
#define CC_PC5_CMOS_OFF_INPUT		0x0C00

#define CC_PC4_MASK			0xFCFF
#define CC_PC4_FUNC_OUTPUT		0x0000
#define CC_PC4_OUTPUT			0x0100
#define CC_PC4_CMOS_ON_INPUT		0x0200
#define CC_PC4_CMOS_OFF_INPUT		0x0300

#define CC_PC3_MASK			0xFF3F
#define CC_PC3_FUNC_OUTPUT		0x0000
#define CC_PC3_OUTPUT			0x0040
#define CC_PC3_CMOS_ON_INPUT		0x0080
#define CC_PC3_CMOS_OFF_INPUT		0x00C0

#define CC_PC2_MASK			0xFFCF
#define CC_PC2_FUNC_OUTPUT		0x0000
#define CC_PC2_OUTPUT			0x0010
#define CC_PC2_CMOS_ON_INPUT		0x0020
#define CC_PC2_CMOS_OFF_INPUT		0x0030

#define CC_PC1_MASK			0xFFF3
#define CC_PC1_FUNC_OUTPUT		0x0000
#define CC_PC1_OUTPUT			0x0004
#define CC_PC1_CMOS_ON_INPUT		0x0008
#define CC_PC1_CMOS_OFF_INPUT		0x000C

#define CC_PC0_MASK			0xFFFC
#define CC_PC0_FUNC_OUTPUT		0x0000
#define CC_PC0_OUTPUT			0x0001
#define CC_PC0_CMOS_ON_INPUT		0x0002
#define CC_PC0_CMOS_OFF_INPUT		0x0003

/****** Value of GPDCR ******/
#define CC_PD7_MASK			0x3FFF
#define CC_PD7_FUNC_OUTPUT		0x0000
#define CC_PD7_OUTPUT			0x4000
#define CC_PD7_CMOS_ON_INPUT		0x8000
#define CC_PD7_CMOS_OFF_INPUT		0xC000

#define CC_PD6_MASK			0xCFFF
#define CC_PD6_FUNC_OUTPUT		0x0000
#define CC_PD6_OUTPUT			0x1000
#define CC_PD6_CMOS_ON_INPUT		0x2000
#define CC_PD6_CMOS_OFF_INPUT		0x3000

#define CC_PD5_MASK			0xF3FF
#define CC_PD5_FUNC_OUTPUT		0x0000
#define CC_PD5_OUTPUT			0x0400
#define CC_PD5_CMOS_ON_INPUT		0x0800
#define CC_PD5_CMOS_OFF_INPUT		0x0C00

#define CC_PD4_MASK			0xFCFF
#define CC_PD4_FUNC_OUTPUT		0x0000
#define CC_PD4_OUTPUT			0x0100
#define CC_PD4_CMOS_ON_INPUT		0x0200
#define CC_PD4_CMOS_OFF_INPUT		0x0300

#define CC_PD3_MASK			0xFF3F
#define CC_PD3_FUNC_OUTPUT		0x0000
#define CC_PD3_OUTPUT			0x0040
#define CC_PD3_CMOS_ON_INPUT		0x0080
#define CC_PD3_CMOS_OFF_INPUT		0x00C0

#define CC_PD2_MASK			0xFFCF
#define CC_PD2_FUNC_OUTPUT		0x0000
#define CC_PD2_OUTPUT			0x0010
#define CC_PD2_CMOS_ON_INPUT		0x0020
#define CC_PD2_CMOS_OFF_INPUT		0x0030

#define CC_PD1_MASK			0xFFF3
#define CC_PD1_FUNC_OUTPUT		0x0000
#define CC_PD1_OUTPUT			0x0004
#define CC_PD1_CMOS_ON_INPUT		0x0008
#define CC_PD1_CMOS_OFF_INPUT		0x000C

#define CC_PD0_MASK			0xFFFC
#define CC_PD0_FUNC_OUTPUT		0x0000
#define CC_PD0_OUTPUT			0x0001
#define CC_PD0_CMOS_ON_INPUT		0x0002
#define CC_PD0_CMOS_OFF_INPUT		0x0003

/* Bits for the STCN6550 AFE master clock select */
#define CC_GPACR_AFE_CLOCK_CONTROL_MASK		0xFFF0
#define CC_GPACR_AFE_CLOCK_CONTROL_SELECT	0x0005
#define CC_GPADR_AFE_CLOCK_MASK			0xFC
#define CC_GPADR_AFE_MODEM_CLOCK		0x03
#define CC_GPADR_AFE_SLOW_CLOCK			0x01
#define CC_GPADR_AFE_FAST_CLOCK			0x02
#define CC_GPADR_AFE_NO_CLOCK			0x00

#define FIR_CFG_OFFSET			0x01E0		/* FIR Configuration Register */

#define CC_FIR_CFG				(UART_REGBASE + 0x01E0)	// cut 5
//#define CC_FIR_CFG				(UART_REGBASE + 0x0120)		// cut 3

/* FIR Configuration bit definitions */
#define FIR_CFG_CLR1			0xFD
#define FIR_CFG_EN02			0x05

#endif