cchal.h

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/*****************************************************************************
*	HEADER_NAME :	cchal.h
*	MODULE :		Companion Chip Specific Definitions (OAL)
*	DESCRIPTION :	This file is created to contain the companion chip ASIC 
*					register defines that are needed by the OAL
*
*	AUTHOR :		Dennis Hunt
*					Tom Newman (tjn), Mission Peak Designs
*	HISTORY :		
*			18-Jul-1997		Created Dennis Hunt
*			5/4/1999	tjn	Modified for HD64465
*
*   DEPENDENCIES: project.h
*
*
*****************************************************************************/

#ifndef CCHAL_H
#define CCHAL_H

/* typedefs and #defines */

/*----------------------------------------------------------------------------/
/* power and system control module */

#define CC_SYS_STBCR		(CC_SYS_REGBASE+CC_SYS_STBCR_OFFSET)	/* standby control register */
#define CC_SYS_SYSCR		(CC_SYS_REGBASE+CC_SYS_SYSCR_OFFSET)	/* system control register */

/* STBCR definitions - 'and' these with CC_SYS_STBCR to enable
 * these operate by enabling the clock to the module
 */
#define CC_STBCR_MIAST_ON		0xFEFF			/* turn on min. card i/f */
#define CC_STBCR_LCDST_ON		0xFF7F			/* turn on LCD  */
#define CC_STBCR_PC0ST_ON		0xFFBF			/* turn on PCMCIA channel 0  */
#define CC_STBCR_PC1ST_ON		0xFFDF			/* turn on PCMCIA channel 1  */
#define CC_STBCR_AFEST_ON		0xFFEF			/* turn on AFE I/F  */
#define CC_STBCR_TM0ST_ON		0xFFF7			/* turn on Timer 0  */
#define CC_STBCR_TM1ST_ON		0xFFFB			/* turn on Timer 1  */
#define CC_STBCR_IRST_ON		0xFFFD			/* turn on IrDA controller  */
#define CC_STBCR_URTST_ON		0xFFFE			/* turn on UART  */

/* 'or' these to disable the module */
#define CC_STBCR_MIAST_OFF		0x0100			/* turn off clock to min. card i/f */
#define CC_STBCR_LCDST_OFF		0x0080			/* turn off LCD  */
#define CC_STBCR_PC0ST_OFF		0x0040			/* turn off PCMCIA channel 0  */
#define CC_STBCR_PC1ST_OFF		0x0020			/* turn off PCMCIA channel 1  */
#define CC_STBCR_AFEST_OFF		0x0010			/* turn off AFE I/F  */
#define CC_STBCR_TM0ST_OFF		0x0008			/* turn off Timer 0  */
#define CC_STBCR_TM1ST_OFF		0x0004			/* turn off Timer 1  */
#define CC_STBCR_IRST_OFF		0x0002			/* turn off IrDA cOFFtroller  */
#define CC_STBCR_URTST_OFF		0x0001			/* turn off UART  */

/* SYSCR definitions
 * these enable different modules/pins in the c.c.
 * MODES: specifies which sets of modules are enabled
 *        00 = PCMCIA0, PCMCIA1, A/IrDA, A/Timer, A1:0, B/UART, AFE. LCD, CRT
 *        01 = PCMCIA0, MIN.CARD, A/IrDA, A/IIC, A1:0, B/UART, AFE, LCD, CRT
 *        10 = PCMCIA0, A/IrDA, A/Timer, A1:0, B/UART, C, D, AFE, LCD, CRT
 *        11 = PCMCIA0, MIN.CARD, A/IrDA, A/IIC, A1:0, B/UART, AFE
 */
#define CC_SYSCR_SPTA_IR_MASK	0xFF7F			/* mask for IR/GPIO */
#define CC_SYSCR_SPTA_IR_IR		0x0080			/* select IR */
#define CC_SYSCR_SPTA_IR_GPIO	0x0000			/* select GPIO (port A7:4) */

#define CC_SYSCR_SPTA_IIC_MASK	0xFFBF			/* mask for IR/GPIO */
#define CC_SYSCR_SPTA_IIC_IIC	0x0040			/* select IR - MODES 11 and 01 only */
#define CC_SYSCR_SPTA_IIC_TIMER	0x0040			/* select TIMER - MODES 10 and 00 only */
#define CC_SYSCR_SPTA_IIC_GPIO	0x0000			/* select GPIO (port A3:0) */

#define CC_SYSCR_SPTB_UR_MASK	0xFFDF			/* mask for UART/GPIO */
#define CC_SYSCR_SPTB_UR_UART	0x0020			/* select UART */
#define CC_SYSCR_SPTB_UR_GPIO	0x0000			/* select GPIO (port B) */

#define CC_SYSCR_MODE_MASK		0xFFFC			/* mask for MODE */
#define CC_SYSCR_MODE_00		0x0000			/* MODE 00 */
#define CC_SYSCR_MODE_01		0x0001			/* MODE 01 */
#define CC_SYSCR_MODE_10		0x0002			/* MODE 10 */
#define CC_SYSCR_MODE_11		0x0003			/* MODE 11 */

/*----------------------------------------------------------------------------/
/* interrupt controller module */

#define CC_INTC_IRR			(CC_INTC_REGBASE+CC_INTC_REQ_OFFSET)	/* main interrupt request register */
#define CC_INTC_IMR			(CC_INTC_REGBASE+CC_INTC_MASK_OFFSET)	/* main interrupt mask register */

/* INTC IRR bit definitions (** cea 6/3/99) */

#define INTC_IRR_PS2KBR			0x8000			/* PS/2 Keyboard interrupt */
#define INTC_IRR_PCC0R			0x4000			/* PCC0R interrupt */
#define INTC_IRR_PCC1R			0x2000			/* PCC1R interrupt */
#define INTC_IRR_AFER			0x1000			/* AFER interrupt */
#define INTC_IRR_GPIOR			0x0800			/* GPIOR interrupt */
#define INTC_IRR_TMU0R			0x0400			/* TMU0R interrupt */
#define INTC_IRR_TMU1R			0x0200			/* TMU1R interrupt */
#define INTC_IRR_KBCR			0x0100			/* H8 (keyboar/mouse controller) interrupt */
#define INTC_IRR_PS2MSR			0x0080			/* PS/2 mouse interrupt */
#define INTC_IRR_IRDAR			0x0040			/* IRDAR interrupt */
#define INTC_IRR_UARTR			0x0020			/* UARTR interrupt */
#define INTC_IRR_USB			0x0002			/* USB interrupt */

/* INTC IMR bit definitions (** cea 6/3/99) */
#define INTC_IMR_ALL_MASK		0xFFFF			/* mask all interrupts from CC */

#define INTC_IMR_PS2KBM_MASK	0x8000			/* PS/2 Keyboard mask */
#define INTC_IMR_PCC0M_MASK		0x4000			/* PCC0R interrupt mask */
#define INTC_IMR_PCC1M_MASK		0x2000			/* PCC1R interrupt mask */
#define INTC_IMR_AFEM_MASK		0x1000			/* AFER interrupt mask */
#define INTC_IMR_GPIOM_MASK		0x0800			/* GPIOR interrupt mask */
#define INTC_IMR_TMU0M_MASK		0x0400			/* TMU0R interrupt mask */
#define INTC_IMR_TMU1M_MASK		0x0200			/* TMU1R interrupt mask */
#define INTC_IMR_KBCM_MASK		0x0100			/* H8 (keyboar/mouse controller) mask */
#define INTC_IMR_PS2MSM_MASK	0x0080			/* PS/2 mouse mask */
#define INTC_IMR_IRDAM_MASK		0x0040			/* IRDAR interrupt mask */
#define INTC_IMR_UARTM_MASK		0x0020			/* UARTR interrupt mask */
#define INTC_IMR_USB_MASK		0x0002			/* USB interrupt mask */

#define INTC_IMR_PS2KBM_UNMASK	0x7FFF			/* PS/2 Keyboard UNmask */
#define INTC_IMR_PCC0M_UNMASK	0xBFFF			/* PCC0R interrupt UNmask */
#define INTC_IMR_PCC1M_UNMASK	0xDFFF			/* PCC1R interrupt UNmask */
#define INTC_IMR_AFEM_UNMASK	0xEFFF			/* AFER interrupt UNmask */
#define INTC_IMR_GPIOM_UNMASK	0xF7FF			/* GPIOR interrupt UNmask */
#define INTC_IMR_TMU0M_UNMASK	0xFBFF			/* TMU0R interrupt UNmask */
#define INTC_IMR_TMU1M_UNMASK	0xFDFF			/* TMU1R interrupt UNmask */
#define INTC_IMR_KBCM_UNMASK	0xFEFF			/* H8 (keyboar/mouse controller) UNmask */
#define INTC_IMR_PS2MSM_UNMASK	0xFF7F			/* PS/2 mouse UNmask */
#define INTC_IMR_IRDAM_UNMASK	0xFFBF			/* IRDAR interrupt UNmask */
#define INTC_IMR_UARTM_UNMASK	0xFFDF			/* UARTR interrupt UNmask */
#define INTC_IMR_USB_UNMASK		0xFFFD			/* USB interrupt UNmask */


/*
 * Keyboard and Mouse(AUX) port interface.
 *
 * Supports the PS/2 port in the HD64465 companion chip
 *
 * (** cea 6/3/99)
 */

 /*
 * Keyboard (HD64465) defines 
 */
#define KB_BASE 			(SYSTEM_ASIC_REGS_BASE + ASIC_KBC_OFFSET)
#define KB_ISR				0x0C04		/* offset from keyboard base reg */
#define KB_CSR				0x0C00		/* offset from keyboard base reg */
#define KB_INTR_MASK		0x0001
#define KB_RDRF 			0x0001
#define KB_PARITY			0x0100			
#define KB_DATA_RD			0x0200
#define KB_CLK_RD			0x0400
#define KB_DATA_DR			0x0800
#define KB_CLK_DR			0x1000
#define KB_DATA_DR_EN		0x2000
#define KB_CLK_DR_EN		0x4000
#define KB_CLK_EN			0x8000

/* 
 * Mouse (HD64465) defines
 *
 * This version has the mouse base address equal 
 * to the keyboard base address.
 */
#define MOUSE_BASE			(SYSTEM_ASIC_REGS_BASE + ASIC_KBC_OFFSET)
#define MOUSE_ISR			0x0C14		/* offset from keyboard base reg */
#define MOUSE_CSR			0x0C10		/* offset from keyboard base reg */
#define MOUSE_INTR_MASK 	0x0001
#define MOUSE_RDRF			0x0001
#define MOUSE_PARITY		0x0100			
#define MOUSE_DATA_RD		0x0200
#define MOUSE_CLK_RD		0x0400
#define MOUSE_DATA_DR		0x0800
#define MOUSE_CLK_DR		0x1000
#define MOUSE_DATA_DR_EN	0x2000
#define MOUSE_CLK_DR_EN 	0x4000
#define MOUSE_CLK_EN		0x8000

/*----------------------------------------------------------------------------/
/* Timer module */

/* absolute address, use when available (in kernel mode) */
#define CC_TMR_TCVR1	(TMR_REGBASE+TMR_TCVR1_OFFSET)			/* Constant 1 */
#define CC_TMR_TCVR0	(TMR_REGBASE+TMR_TCVR0_OFFSET)			/* Constant 0 */
#define CC_TMR_TRVR1	(TMR_REGBASE+TMR_TRVR1_OFFSET)			/* Read Count 1 */
#define CC_TMR_TRVR0	(TMR_REGBASE+TMR_TRVR0_OFFSET)			/* Read Count 0 */
#define CC_TMR_TCR1		(TMR_REGBASE+TMR_TCR1_OFFSET)			/* Control 1 */
#define CC_TMR_TCR0		(TMR_REGBASE+TMR_TCR0_OFFSET)			/* Control 0 */
#define CC_TMR_TIRR		(TMR_REGBASE+TMR_TIRR_OFFSET)			/* Interrupt Request */
#define CC_TMR_TIMR		(TMR_REGBASE+TMR_TIMR_OFFSET)			/* Interrupt Mask */

/* timer control register bit definitions */
/* these are identical for both control registers */
#define TMR_TCR_EMTO_MASK		0xFFF7			/* isloate EMTO */
#define TMR_TCR_EMTO_ENABLE		0x0008			/* set EMTO */
#define TMR_TCR_EMTO_DISABLE	0x0000			/* clear EMTO */
#define TMR_TCR_PST_MASK		0xFFF9			/* isolate PST */
#define TMR_TCR_PST_CLK_DIV_16	0x0000			/* ckio/16 */
#define TMR_TCR_PST_CLK_DIV_8	0x0002			/* ckio/8 */
#define TMR_TCR_PST_CLK_DIV_4	0x0004			/* ckio/4 */
#define TMR_TCR_PST_CLK_DIV_1	0x0006			/* ckio/1 */
#define TMR_TCR_TSTP_BITS		0x0001			/* bit(s) user for the timer start/stop */
#define TMR_TCR_TSTP_MASK		0xFFFE			/* isolate TSTP */
#define TMR_TCR_TSTP_START		0x0001			/* start timer */
#define TMR_TCR_TSTP_STOP		0x0000			/* stop timer */

/* Interrupt request register bit definitions */
#define TMR_TIRR_TMU0R_MASK		0xFFFE			/* timer 0 interrupt request mask */
#define TMR_TIRR_TMU0R_ENABLE	0x0001			/* timer 0 interrupt request occurred */
#define TMR_TIRR_TMU0R_DISABLE	0x0000			/* timer 0 interrupt request clear*/
#define TMR_TIRR_TMU1R_MASK		0xFFFD			/* timer 1 interrupt request mask */
#define TMR_TIRR_TMU1R_ENABLE	0x0002			/* timer 1 interrupt request occurred */
#define TMR_TIRR_TMU1R_DISABLE	0x0000			/* timer 1 interrupt request clear */

/* Interrupt mask register bit definitions */
#define TMR_TIMR_TMU0M_MASK		0xFFFE			/* timer 0 interrupt mask */
#define TMR_TIMR_TMU0M_ENABLE	0x0001			/* timer 0 interrupt enable */
#define TMR_TIMR_TMU0M_DISABLE	0x0000			/* timer 0 interrupt disable */
#define TMR_TIMR_TMU1M_MASK		0xFFFD			/* timer 1 interrupt mask */
#define TMR_TIMR_TMU1M_ENABLE	0x0002			/* timer 1 interrupt enable */
#define TMR_TIMR_TMU1M_DISABLE	0x0000			/* timer 1 interrupt disable */

/*----------------------------------------------------------------------------/
/* AFE module */

/* absolute addresses when in kernel mode */
#define CC_AFE_ARXDBR0		(CC_AFE_REGBASE+CC_AFE_ARXDBR0_OFFSET)			/* Receive buffer 0 */
#define CC_AFE_ARXDBR1		(CC_AFE_REGBASE+CC_AFE_ARXDBR1_OFFSET)			/* Receive buffer 1 (same offset!) */
#define CC_AFE_ATXDBR0		(CC_AFE_REGBASE+CC_AFE_ATXDBR0_OFFSET)			/* Transmit buffer 0 */
#define CC_AFE_ATXDBR1		(CC_AFE_REGBASE+CC_AFE_ATXDBR1_OFFSET)			/* Transmit buffer 1 (same offset!) */
#define CC_AFE_ACTR			(CC_AFE_REGBASE+CC_AFE_ACTR_OFFSET)				/* Control register */
#define CC_AFE_ASTR			(CC_AFE_REGBASE+CC_AFE_ASTR_OFFSET)				/* Status register */
#define CC_AFE_ARXDR		(CC_AFE_REGBASE+CC_AFE_ARXDR_OFFSET)			/* Receive data register */
#define CC_AFE_ATXDR		(CC_AFE_REGBASE+CC_AFE_ATXDR_OFFSET)			/* Transmit data register */

/* ACTR control register bit definitions */
#define CC_AFE_ACTR_HC		0x8000				/* program AFE control register (auto clears) */
#define CC_AFE_ACTR_DIV2	0x4000
#define CC_AFE_ACTR_DIV1	0x2000
#define CC_AFE_ACTR_RLY		0x1000
#define CC_AFE_ACTR_CNT2	0x0800				/* Power: on(1) off(0) */
#define CC_AFE_ACTR_CNT1	0x0400				/* Reset: OPERATE(1) RESET(0) */
#define CC_AFE_ACTR_TSW		0x0200
#define CC_AFE_ACTR_RSW		0x0100
#define CC_AFE_ACTR_RDETM	0x0080				/* Ring Detect interrupt disable!?!? */
#define CC_AFE_ACTR_TEIE	0x0040				/* Transmit error interrupt enable */
#define CC_AFE_ACTR_REIR	0x0020				/* Receive error interrupt enable */
#define CC_AFE_ACTR_TXIE	0x0010				/* Transmit data empty interrupt enable */
#define CC_AFE_ACTR_RXIR	0x0008				/* Receive data full interrupt enable */
#define CC_AFE_ACTR_BUFD	0x0004				/* Buffer disable: use register(1) buffer(0) */
#define CC_AFE_ACTR_TE		0x0002				/* Transmit enable */
#define CC_AFE_ACTR_RE		0x0001				/* Receive enable */

/* ASTR status register bit definitions */
#define CC_AFE_ASTR_TAB		0x8000				/* accessible transmit buffer */
#define CC_AFE_ASTR_RAB		0x4000				/* accessible receive buffer */
#define CC_AFE_ASTR_TERR	0x0008				/* transmit underrun error */
#define CC_AFE_ASTR_RERR	0x0004				/* receive overrun error */
#define CC_AFE_ASTR_TDE		0x0002				/* transmit buffer empty */
#define CC_AFE_ASTR_RDF		0x0001				/* receive buffer full */

/*----------------------------------------------------------------------------/
/* FIR (IrDA) and 16550 module
 * There is 1 UART on the companion chip, shared between the UART and FIR module.
 * The FIR is IrDA 1.1 capable, and so has more definitions
 * to implement when IrDA 1.1 is available in Windows CE
 * The UART is a straight 16550 UART 
 */
#define UART_REGBASE			(SYSTEM_ASIC_REGS_BASE+ASIC_FIR_OFFSET)
#define UART_OFFSET				(ASIC_UART_OFFSET-ASIC_FIR_OFFSET)

/* Additions -- Naresh Gupta
 * Added the following from S1a004 to support FIR
 */

#define FIR_REGBASE			(SYSTEM_ASIC_REGS_BASE+ASIC_FIR_OFFSET)
#define FIR_OFFSET				(ASIC_UART_OFFSET-ASIC_FIR_OFFSET)
#define FIR_REGSIZE            0x10


/* Settings */
#define BANKSELECT0			   0xE0         /* #S1_FIR Select Bank 0 */
#define BANKSELECT1			   0xE1         /* #S1_FIR Select Bank 0 */
#define BANKSELECT2			   0xE2         /* #S1_FIR Select Bank 0 */
#define TXEN_ON				   0x40         /* #S1_FIR TXEN bit On */
#define TXEN_OFF			   0x5F         /* #S1_FIR TXEN bit Off */
#define RXEN_ON				   0x20         /* #S1_FIR RXEN bit On */
#define RXEN_OFF			   0xDF         /* #S1_FIR RXEN bit Off */
#define RSTC_RFP			   0x20         /* #S1_FIR Rx FIFO Pointer Reset */
#define RSTC_TFP			   0x60         /* #S1_FIR Tx FIFO Pointer Reset */
#define EEIL_ON				   0x00         /* #S1_FIR EEIL bit On */
#define EEIL_OFF			   0xF8         /* #S1_FIR EEIL bit Off */
#define ISIRR_4M_MODE		   0x00			/* #S1_FIR Set ISIRR to 4M Mode */
#define RFRIEN_ON              0x02			/* #S1_FIR RFRIEN bit in IRCR On */
#define RFRIEN_OFF             0xFD			/* #S1_FIR RFRIEN bit in IRCR Off */
#define TFRIEN_ON              0x40			/* #S1_FIR TFRIEN bit in ITC1R On */
#define TFRIEN_OFF			   0xBF			/* #S1_FIR TFRIEN bit in ITC1R Off */