my_pci.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*****************************************************************************
 * File:    pci.h
 * Purpose: Definitions related to Pci.
 * Author:  Naresh Gupta ([e-mail])
 * Date:    July 20, 1998
 ****************************************************************************/

// PCI memory areas.
#define PHYSICAL_PCI_CONTROL 	0xba000000	// PCI control register.
#define PHYSICAL_PCI_IO			0xb8000000	// PCI I/O area
#define PHYSICAL_PCI_MEM		0xb9000000	// PCI memory mapped area.

// PCI Classes of Devices.
#define PCI_CLASS_UNKNOWN							0x00
#define PCI_CLASS_MASS_STORAGE_CONTROLLER			0x01
#define PCI_CLASS_NETWORK_CONTROLLER				0x02
#define PCI_CLASS_DISPLAY_CONTROLLER				0x03
#define PCI_CLASS_MULTIMEDIA_DEVICE					0x04
#define PCI_CLASS_MEMORY_CONTROLLER					0x05
#define PCI_CLASS_BRIDGE_DEVICE						0x06
#define PCI_CLASS_SIMPLE_COMMUNICATIONS_CONTROLLER	0x07
#define PCI_CLASS_BASE_SYSTEM_PERIPHERALS			0x08
#define PCI_CLASS_INPUT_DEVICES						0x09
#define PCI_CLASS_DOCKING_STATIONS					0x0a
#define PCI_CLASS_PROCESSORS						0x0b
#define PCI_CLASS_SERIAL_BUS_CONTROLLERS			0x0c
#define PCI_CLASS_RESERVED							0x0d
#define PCI_CLASS_UNDEFINED							0x0e

// Instance numbers for the devices.
#define PCI_FIRST_INSTANCE							0x0
#define PCI_SECOND_INSTANCE							0x1
#define PCI_THIRD_INSTANCE							0x2
#define PCI_FOURTH_INSTANCE							0x3
#define PCI_FIFTH_INSTANCE							0x4

// This structure will contain the Mapped base addresses for Pci Io/Mem/Control Registers.
// This contains the virtual addresses.
struct PciBaseAddresses_Type {
	unsigned PciIoBase;
	unsigned PciMemBase;
	// unsigned PciControlBase;
};

struct PciDeviceType {
	USHORT	VendorID;
	USHORT	DeviceID;
	USHORT	Command;
	USHORT	Status;
	UCHAR	RevisionID;
	UCHAR	ProgrammingInterfaceCode;
	UCHAR	SubClassCode;
	UCHAR	BaseClassCode;
	UCHAR	CacheLineSize;
	UCHAR	LatencyTimer;
	UCHAR	HeaderType;
	UCHAR	BIST;
	ULONG	BaseAddressRegister[6]; 
	ULONG   Size[6];				// Size of space allocated to each Base Address register.
	UCHAR	InterruptPin;
	UCHAR	InterruptLine;
	ULONG	PhysicalPciIoReg;		// Starting Address of PCI Io space.
	ULONG	PhysicalPciMemReg;		// Starting Address of PCI Mem space.
	ULONG	PhysicalPciControlReg;	// Address of Pci Control Register.
	USHORT	LogInterrupt;			// Logical Interrupt Assigned to this device.
}; 


// Functions which the Pci Dll exports.
struct PciDeviceType *PciScan(unsigned Type, unsigned Instance);
struct PciBaseAddresses_Type *PciGetMappedBaseAddresses(void);