oempci.c
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C语言 代码 · 共 1,258 行 · 第 1/4 页
C
1,258 行
/* the assumption that bus 0 is the one connected to the PCI host bridge. */
if (dwBusNo == 0) {
*pdwAddress = (0x00000800 << dwDevNo) | (dwFuncNo << 8) | (dwOffset & 0xFC);
}
else {
/* Generate a Type 1 address for everything not on Bus 0. */
*pdwAddress = (dwBusNo << 16) | (dwDevNo << 11) | (dwFuncNo << 8) | (dwOffset & 0xFC) | 1;
}
} /* OEM_EncodeConfigAddress */
void OEM_GetPCIHostBridgeStatus( WORD *pwStatus ) {
CONFIG_WAIT;
*pwStatus = (WORD) ((V3_PCI_STAT_CMD >> 16) & PCIE_MASK);
RETAILMSG(1, (TEXT("+GetPCIHBS returning 0x%x\n"), (unsigned) *pwStatus));
#if 0
/// DbgPrintf("GetPCIHostBridgeStatus. Error. Status = 0x%x\n", *pwStatus);
if(*pwStatus) {
DbgPrintf("GetPCIHostBridgeStatus. Error. Status = 0x%x\n", *pwStatus);
}
#endif 0
#if 0
volatile WORD *pwPCIHostBridgeStatusReg = (volatile WORD *)PCI_HOST_BRIDGE_STATUS_REG_ADDR;
*pwStatus = *pwPCIHostBridgeStatusReg & PCIE_MASK;
#endif
} /* OEM_GetPCIHostBridgeStatus */
/* This routine will clear the bus error status bits in the host bridge. */
void OEM_ClearPCIHostBridgeStatus( void ) {
DWORD StatCmd;
// config_wait = CONFIG_WAIT;
// while ( -- config_wait ) ;
StatCmd = V3_PCI_STAT_CMD;
DEBUGMSG(DEB_PCI_CONFIG,(TEXT("+ClearPCIHBS: ORG: PCI_STAT_CMD = 0x%X "), V3_PCI_STAT_CMD));
// Check whether the error got cleared.
if( (StatCmd & 0xFFFF) != 0x246) {
DEBUGMSG(DEB_PCI_CONFIG, (TEXT("OEM_ClearPCIHostBridgeStatus: Fatal error: Unexpected valud of V3 command register\r\n")));
DEBUGMSG(DEB_PCI_CONFIG, (TEXT("V3 command register reads, expected value = 0x246\r\n"), StatCmd));
}
StatCmd |= (PCIE_MASK << 16);
// config_wait = CONFIG_WAIT;
// while ( -- config_wait ) ;
V3_PCI_STAT_CMD = StatCmd;
RETAILMSG(1, (TEXT("+ClearPCIHBS PCI_STAT_CMD = 0x%X\n"), V3_PCI_STAT_CMD));
// config_wait = CONFIG_WAIT;
// while ( -- config_wait ) ;
StatCmd = V3_PCI_STAT_CMD;
StatCmd = StatCmd >> 16;
if( StatCmd != 0x0000 ) {
DbgPrintf("OEM_ClearPCIHostBridgeStatus could not clear. StatCmd = 0x%X\n", StatCmd);
DbgPrintf("V3 Status command register reads, expected value = 0x246\r\n", StatCmd);
DbgPrintf("Breaking into debugger...\r\n");
ProcessCommands();
}
#if 0
volatile WORD *pwPCIHostBridgeStatusReg = (volatile WORD *)PCI_HOST_BRIDGE_STATUS_REG_ADDR;
*pwPCIHostBridgeStatusReg = PCIE_MASK;
#endif
} /* OEM_ClearPCIHostBridgeStatus() */
int OEM_SetPCIHostBridgeWindows( PCIMapInfoRec *pPCIMapInfo ) {
// PCIHostBridgeWindowInfoRec PCIHostBridgeWindowInfo;
DEBUGMSG(DEB_PCI_INIT,(TEXT("OEM_SetPCIHBW: MemBase=0x%x, MemLimit=0x%x, IOBase=0x%x, IOLimit=0x%x\n"),
pPCIMapInfo->dwPCIMemBase, pPCIMapInfo->dwPCIMemLimit,
pPCIMapInfo->dwPCIIOBase, pPCIMapInfo->dwPCIIOLimit));
#if ( (SH_PLATFORM == PLATFORM_ASPEN) || (SH_PLATFORM == PLATFORM_BIGSUR) )
// Map the upper bits 15-4 to the LB_MAP1_RES register.
V360_LB_MAP1_RES = (V360_LB_MAP1_RES & 0xF0000) | (pPCIMapInfo->dwPCIMemBase & 0xFFF00000);
DEBUGMSG(1,(TEXT("Set V360_LB_MAP1_RES to 0x%x\n"), V360_LB_MAP1_RES));
#endif (SH_PLATFORM == PLATFORM_ASPEN)
#if 0
volatile DWORD *pdwPriOutboundMemValReg = (volatile DWORD *)0x00001254;
volatile DWORD *pdwPriOutboundIOValReg = (volatile DWORD *)0x0000125C;
*pdwPriOutboundMemValReg = pPCIMapInfo->dwPCIMemBase;
*pdwPriOutboundIOValReg = pPCIMapInfo->dwPCIIOBase;
/* The memory and I/O Limit values are fixed for this processor, */
/* Return an error if the request size exceeds the maximum values. */
/* If the Limit value is less than the Base value it means that */
/* they are closing the windows. Do this if possible, but do not */
/* return an error. */
OEM_GetPCIHostBridgeWindowInfo( &PCIHostBridgeWindowInfo );
if (pPCIMapInfo->dwPCIMemLimit >= pPCIMapInfo->dwPCIMemBase &&
pPCIMapInfo->dwPCIMemLimit - pPCIMapInfo->dwPCIMemBase > PCIHostBridgeWindowInfo.dwMemWinSize) {
DbgPrintf( "OEM_SetPCIHostBridgeWindows() - ERROR: Requested Memory Window Size Exceeds Max.\n" );
return 1;
}
if (pPCIMapInfo->dwPCIIOLimit >= pPCIMapInfo->dwPCIIOBase &&
pPCIMapInfo->dwPCIIOLimit - pPCIMapInfo->dwPCIIOBase > PCIHostBridgeWindowInfo.dwIOWinSize) {
DbgPrintf( "OEM_SetPCIHostBridgeWindows() - ERROR: Requested I/O Window Size Exceeds Max.\n" );
return 1;
}
#endif
return 0;
} /* OEM_SetPCIHostBridgeWindows() */
/* JUNK */
#ifdef JUNK
/* These registers are not needed. */
#if 0
#define V3_PCI_IO_BASE *(volatile unsigned long*)(0x10+V3_INTERNAL_REG_BASE)
#define V3_PCI_BASE0 *(volatile unsigned long*)(0x14+V3_INTERNAL_REG_BASE)
#define V3_PCI_BASE1 *(volatile unsigned long*)(0x18+V3_INTERNAL_REG_BASE)
#define V3_PCI_SUB_VEND *(volatile unsigned long*)(0x2c+V3_INTERNAL_REG_BASE)
#define V3_PCI_ROM *(volatile unsigned long*)(0x30+V3_INTERNAL_REG_BASE)
#define V3_PCI_BPARAM *(volatile unsigned long*)(0x3c+V3_INTERNAL_REG_BASE)
#define V3_PCI_MAP0 *(volatile unsigned long*)(0x40+V3_INTERNAL_REG_BASE)
#define V3_PCI_MAP1 *(volatile unsigned long*)(0x44+V3_INTERNAL_REG_BASE)
#define V3_PCI_INT_STAT *(volatile unsigned long*)(0x48+V3_INTERNAL_REG_BASE)
#define V3_PCI_INT_CFG *(volatile unsigned long*)(0x4c+V3_INTERNAL_REG_BASE)
#define V3_LB_IM_IS_STAT *(volatile unsigned long*)(0x74+V3_INTERNAL_REG_BASE)
#endif
#if 0
#define V3_PCI_VENDOR (0x00 + V3_INTERNAL_REG_BASE)
#define V3_PCI_DEVICE_ID (0x02 + V3_INTERNAL_REG_BASE)
#define V3_PCI_CMD (0x04 + V3_INTERNAL_REG_BASE)
#define V3_PCI_STAT (0x06 + V3_INTERNAL_REG_BASE)
#define V3_PCI_CC_REV (0x08 + V3_INTERNAL_REG_BASE)
#define V3_PCI_HDR_CFG (0x0c + V3_INTERNAL_REG_BASE)
#define V3_PCI_IO_BASE (0x10 + V3_INTERNAL_REG_BASE) // This is PCI_I20_BASE in V320
#define V3_PCI_BASE0 (0x14 + V3_INTERNAL_REG_BASE)
#define V3_PCI_BASE1 (0x18 + V3_INTERNAL_REG_BASE)
#define V3_PCI_SUB_VENDOR (0x2c + V3_INTERNAL_REG_BASE)
#define V3_PCI_SUB_ID (0x2e + V3_INTERNAL_REG_BASE)
#define V3_PCI_ROM (0x30 + V3_INTERNAL_REG_BASE)
#define V3_PCI_BPARAM (0x3c + V3_INTERNAL_REG_BASE)
#define V3_PCI_MAP0 (0x40 + V3_INTERNAL_REG_BASE)
#define V3_PCI_MAP1 (0x44 + V3_INTERNAL_REG_BASE)
#define V3_PCI_INT_STAT (0x48 + V3_INTERNAL_REG_BASE)
#define V3_PCI_INT_CFG (0x4c + V3_INTERNAL_REG_BASE)
#define V3_LB_BASE0 (0x54 + V3_INTERNAL_REG_BASE)
#define V3_LB_BASE1 (0x58 + V3_INTERNAL_REG_BASE)
#define V3_LB_MAP0 (0x5e + V3_INTERNAL_REG_BASE)
#define V3_LB_MAP1 (0x62 + V3_INTERNAL_REG_BASE)
#define V3_LB_IOBASE (0x6e + V3_MEM_AREA) // I Don't know how this register is visible here.
#define V3_FIFO_CFG (0x70 + V3_INTERNAL_REG_BASE)
#define V3_FIFO_PRIORITY (0x72 + V3_INTERNAL_REG_BASE)
#define V3_FIFO_STAT (0x74 + V3_INTERNAL_REG_BASE)
#define V3_LB_ISTAT (0x76 + V3_INTERNAL_REG_BASE)
#define V3_LB_IMASK (0x77 + V3_INTERNAL_REG_BASE)
#define V3_SYSTEM (0x78 + V3_INTERNAL_REG_BASE)
#define V3_LB_CFG (0x7b + V3_INTERNAL_REG_BASE)
#define V3_LB_CFG (0x7b + V3_INTERNAL_REG_BASE)
#endif
#if 0
DbgPrintf("SDB PCI Testing Software Version 1.0\n" );
DbgPrintf("463 SMSCR= %08x\r\n", READ_REGISTER_USHORT(0xB0000000));
DbgPrintf("463 SCR= %08x\r\n", READ_REGISTER_USHORT(0xB0000002));
DbgPrintf("463 SBCR= %08x\r\n", READ_REGISTER_USHORT(0xB0000004));
DbgPrintf("463 SPCCR= %08x\r\n", READ_REGISTER_USHORT(0xB0000006));
DbgPrintf("463 SPSWRCR= %08x\r\n", READ_REGISTER_USHORT(0xB0000008));
DbgPrintf("463 SPLLCR= %08x\r\n", READ_REGISTER_USHORT(0xB000000A));
DbgPrintf("463 SRR= %08x\r\n", READ_REGISTER_USHORT(0xB000000C));
DbgPrintf("463 STMCR= %08x\r\n", READ_REGISTER_USHORT(0xB000000E));
DbgPrintf("465 SMSCR= %08x\r\n", READ_REGISTER_USHORT(0xA8000000));
DbgPrintf("465 SCR= %08x\r\n", READ_REGISTER_USHORT(0xA8000002));
DbgPrintf("465 SBCR= %08x\r\n", READ_REGISTER_USHORT(0xA8000004));
DbgPrintf("465 SPCCR= %08x\r\n", READ_REGISTER_USHORT(0xA8000006));
DbgPrintf("465 SPSWRCR= %08x\r\n", READ_REGISTER_USHORT(0xA8000008));
DbgPrintf("465 SPLLCR= %08x\r\n", READ_REGISTER_USHORT(0xA800000A));
DbgPrintf("465 SRR= %08x\r\n", READ_REGISTER_USHORT(0xA800000C));
DbgPrintf("465 STMCR= %08x\r\n", READ_REGISTER_USHORT(0xA800000E));
DbgPrintf("MExINT= %08x\r\n", READ_REGISTER_USHORT(MExINT));
DbgPrintf("ExINT= %08x\r\n", READ_REGISTER_USHORT(ExINT));
DbgPrintf("FRQCR= %08x\r\n", READ_REGISTER_USHORT(FRQCR));
DbgPrintf("BCR1= %08x\r\n", READ_REGISTER_ULONG(BCR1));
DbgPrintf("BCR2= %08x\r\n", READ_REGISTER_USHORT(BCR2));
DbgPrintf("WCR1= %08x\r\n", READ_REGISTER_ULONG(WCR1));
DbgPrintf("WCR2= %08x\r\n", READ_REGISTER_ULONG(WCR2));
DbgPrintf("WCR3= %08x\r\n", READ_REGISTER_ULONG(WCR3));
DbgPrintf("MCR= %08x\r\n", READ_REGISTER_ULONG(MCR));
#endif
#endif
//////////////////////////////////////////////////////////////////////////
//
// $Header: /Windows CE/BigSur/drivers/my_pci/oempci.c 2 7/13/00 3:13p Ngupta $
/* $History: oempci.c $
*
* ***************** Version 2 *****************
* User: Ngupta Date: 7/13/00 Time: 3:13p
* Updated in $/Windows CE/BigSur/drivers/my_pci
* Intermediate check in.
*
* ***************** Version 1 *****************
* User: Mrastogi Date: 6/20/00 Time: 5:20p
* Created in $/Windows CE/BigSur/drivers/my_pci
* Base Version received from HCL Noida on June 07, 2000.
/* */
/* ***************** Version 26 ***************** */
/* User: Ngupta Date: 1/07/00 Time: 4:41p */
/* Updated in $/WINCE211/PLATFORM/ASPEN/drivers/my_pci */
/* Intermediate/temporary checkin to move to Wince 2.12 */
/* */
/* ***************** Version 22 ***************** */
/* User: Ngupta Date: 10/11/99 Time: 10:55a */
/* Updated in $/WINCE211/PLATFORM/ASPEN/drivers/my_pci */
/* */
/* ***************** Version 21 ***************** */
/* User: Ngupta Date: 10/06/99 Time: 10:01a */
/* Updated in $/WINCE211/PLATFORM/ASPEN/drivers/my_pci */
/* Working Keyboard, Mouse, 64464 In CS4 */
/* */
/* ***************** Version 20 ***************** */
/* User: Ngupta Date: 9/15/99 Time: 11:30a */
/* Updated in $/WINCE211/PLATFORM/ASPEN/SDBTEST/SDBTEST */
/* Checked in to Move from 2.11 to 2.12 */
/* */
/* ***************** Version 19 ***************** */
/* User: Ngupta Date: 9/07/99 Time: 10:07a */
/* Updated in $/Wince210/PLATFORM/MY_S1/BOOTLOAD/SDBTEST */
/* Tried merging Windows CE and SDBTEST code. */
/* */
/* ***************** Version 18 ***************** */
/* User: Ngupta Date: 9/03/99 Time: 10:23a */
/* Updated in $/WINCE211/PLATFORM/ASPEN/drivers/my_pci */
/* Working Display driver. */
/* The system hangs in MAXALL after running for sometime. */
/* MINGDI is fine. */
/* */
/* ***************** Version 17 ***************** */
/* User: Ngupta Date: 8/26/99 Time: 12:40p */
/* Updated in $/WINCE211/PLATFORM/ASPEN/drivers/my_pci */
/* Lot of Delays. */
/* Need to remove and replace by a macro. */
/* */
/* ***************** Version 16 ***************** */
/* User: Ngupta Date: 8/25/99 Time: 11:10a */
/* Updated in $/WINCE211/PLATFORM/ASPEN/drivers/my_pci */
/* PCI Enumeration working. */
/* */
/* ***************** Version 15 ***************** */
/* User: Ngupta Date: 8/24/99 Time: 12:10p */
/* Updated in $/WINCE211/PLATFORM/ASPEN/Kernel/hal/shx */
/* Removed a few warnings. */
/* */
/* ***************** Version 14 ***************** */
/* User: Ngupta Date: 8/23/99 Time: 12:35p */
/* Updated in $/Wince210/PLATFORM/MY_S1/BOOTLOAD/SDBTEST */
/* Memory Tests working. */
/* Only for Type 1 writes, i need to write, delay, write instead of single */
/* write. */
/* */
/* ***************** Version 13 ***************** */
/* User: Ngupta Date: 8/13/99 Time: 3:45p */
/* Updated in $/Wince210/PLATFORM/MY_S1/BOOTLOAD/SDBTEST */
/* All PCI Tests working with Delay & Debug Messages */
/* */
/* ***************** Version 12 ***************** */
/* User: Ngupta Date: 8/10/99 Time: 6:11p */
/* Updated in $/Wince210/PLATFORM/MY_S1/BOOTLOAD/SDBTEST */
/* Not working. PCI Memory has problems */
/* program gets corrupted */
/* */
/* ***************** Version 11 ***************** */
/* User: Ngupta Date: 7/19/99 Time: 9:26a */
/* Updated in $/Wince210/PLATFORM/MY_S1/BOOTLOAD/SDBTEST */
/* Intermediate working version */
/* */
/* ***************** Version 10 ***************** */
/* User: Ngupta Date: 7/12/99 Time: 5:23p */
/* Updated in $/Wince210/PLATFORM/MY_S1/BOOTLOAD/SDBTEST */
/* updated comment for idsel. */
/* still working on PCI Memory on RIO */
/* */
/* ***************** Version 9 ***************** */
/* User: Lallen Date: 7/09/99 Time: 12:51p */
/* Updated in $/Wince210/PLATFORM/MY_S1/BOOTLOAD/SDBTEST */
/*////////////////////////////////////////////////////////////////////////*/
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