ndismlib.c

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

	DBGOUT((TEXT("<==NdisMDeregisterDmaChannel")));
}

// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------

ULONG ignoreCOunt = 0;

VOID 
NdisMSetupDmaTransfer(
    PNDIS_STATUS            pStatus,
    PNDIS_HANDLE            phMiniportDmaHandle,
    PNDIS_BUFFER            pBuffer,
    ULONG                   Offset,
    ULONG                   Length,
    BOOLEAN                 WriteToDevice
    )
{
    int   DMAChanOffset;
    PDMA1_CONTROL dmaControl = 0;
    DWORD dwPhysAddress,dwPhysAddressDMARP,dwPhysAddressDMAWP;
	ULONG DataLength;

//    static int ii=0;
//	if(ii==0){
//		SetFirMode();
//#ifdef OUTMSG
//		RETAILMSG(1,(TEXT("SetFirMode\r\n")));
//#endif
//	}
//	ii++;

	//SetFirMode();
#ifdef OUTMSG
	RETAILMSG(0,(TEXT("SetFirMode\r\n")));
#endif

	DBGOUT((TEXT("==>NdisMSetupDmaTransfer")));
	DEBUGMSG(ZONE_FIRMODE, (TEXT("NdisMSetupDmaTransfer -->\r\n")));
    *pStatus = NDIS_STATUS_SUCCESS;

    if (phMiniportDmaHandle != MINIPORT_DMA_HANDLE)
    {
        *pStatus = NDIS_STATUS_RESOURCES;
        goto done;
    }

    DMAChanOffset = g_nDmaChannel;

    if (Offset + Length > pBuffer->BufferLength)
    {
        DBGERR((TEXT("Whoa! The offset+length is greater than the buffer length!")));
        *pStatus = NDIS_STATUS_RESOURCES;
        goto done;
    }
    
    // Get the physical address from virtual address. 
    dwPhysAddress = (DWORD)VirtualToPhysAddress(pBuffer->VirtualAddress) + Offset;
	DataLength = Length;

	if(WriteToDevice){

#ifdef DATALOGDEBUG
		{
			ULONG index;

			RETAILMSG(1, (TEXT("OUT\r\n")));
			for (index = 0; index < DataLength; index++)
			{
				RETAILMSG(1, (TEXT("  0x%x\r\n"), *((PUCHAR) pBuffer->VirtualAddress + Offset + index)));
			}
		}
#endif

		dwPhysAddressDMAWP = (DWORD)CC_FIR_DMAWP;
		WRITE_REGISTER_UCHAR(pITMCR,  CC_FIR_ITMCR_TMCR_66);	// CKIO:66MHz
		WRITE_REGISTER_UCHAR(pIMSTCR, (READ_REGISTER_UCHAR(pIMSTCR) & CC_FIR_IMSTCR_RST_BANK)|CC_FIR_IMSTCR_BANK0);
		WRITE_REGISTER_UCHAR(pIMISCR, CC_FIR_IMISCR_DCS_TX);	// DMA Channel for Tx
		WRITE_REGISTER_UCHAR(pITC2R,  CC_FIR_ITC2R_ACRCG|CC_FIR_ITC2R_SIP_AFTER|CC_FIR_ITC2R_NSFP|CC_FIR_ITC2R_EEIL_EOM);
									// Send Break,transmit a SIP,2 starting flag or a single preamble
		WRITE_REGISTER_UCHAR(pIRSTCR, CC_FIR_IRSTCR_RSTC_TXFIFO);	// Reset Tx FIFO pointer
		WRITE_REGISTER_UCHAR(pIRSTCR, CC_FIR_IRSTCR_RSTC_UNDERRUN);	// Reset FIFO Underrun/EOM Latch
		WRITE_REGISTER_UCHAR(pIMSTCR, (READ_REGISTER_UCHAR(pIMSTCR) & CC_FIR_IMSTCR_RST_BANK) | CC_FIR_IMSTCR_BANK2);// Switch Bank 2
		WRITE_REGISTER_UCHAR(pIIRC2R, CC_FIR_IIRC2R_CHOP_ENABLE_MAX|CC_FIR_IIRC2R_DSIRI);
									// Autochop Enabled with max tolerance for Error,Disable SIR interrupt
		WRITE_REGISTER_UCHAR(pIMSTCR, (READ_REGISTER_UCHAR(pIMSTCR) & CC_FIR_IMSTCR_RST_BANK) | CC_FIR_IMSTCR_BANK1);// Switch Bank 1
		WRITE_REGISTER_UCHAR(pITBCLR, (USHORT)(DataLength) & 0xFF);	// Tx Byte Count Low
		WRITE_REGISTER_UCHAR(pITBCHR, (USHORT)(DataLength) >> 8);		// Tx Byte Count High


		WRITE_REGISTER_ULONG(pSAR0,   dwPhysAddress);			// Source address
		WRITE_REGISTER_ULONG(pDAR0,   dwPhysAddressDMAWP);		// Destination address
		WRITE_REGISTER_ULONG(pDMATCR0,DataLength & 0x0000FFFF);	// Transmit byte length
		READ_REGISTER_ULONG(pCHCR0);				// Reset

/******************************************************************************
 * Modification Done by Maneesh Gupta
 *
 * ASPEN/BIGSUR Related definations has been changed.
 *****************************************************************************/
#if ((SH_PLATFORM == PLATFORM_ASPEN)||(SH_PLATFORM==PLATFORM_BIGSUR))
		WRITE_REGISTER_ULONG(pCHCR0,  DMAC_CHCR_DS_FALLING_EDGE | DMAC_CHCR_RL_ACTIVE_HIGH|DMAC_CHCR_AM_WRITE_CYCLE|DMAC_CHCR_SM_INCREMENTED|DMAC_CHCR_TS_8|DMAC_CHCR_DE_ENABLED);
													// DRAK High, DACK Lo,
													// Source address increase,
													// Transmit size 8bit,
													// DMAC Enable
		READ_REGISTER_ULONG(pDMAOR);				// Reset
		
		WRITE_REGISTER_ULONG(pDMAOR, 0);	// Run
		while(READ_REGISTER_ULONG(pDMAOR)!=0)
		{
			WRITE_REGISTER_ULONG(pDMAOR,  DMAC_DMAOR_DME);	// Run
		}
		WRITE_REGISTER_ULONG(pDMAOR,  DMAC_DMAOR_DME);	// Run
#else // (SH_PLATFORM == PLATFORM_ASPEN)
		WRITE_REGISTER_ULONG(pCHCR0,  SH3_DMAC_CHCR_DS_FALLING_EDGE | SH3_DMAC_CHCR_RL_ACTIVE_HIGH|SH3_DMAC_CHCR_AM_WRITE_CYCLE|SH3_DMAC_CHCR_SM_INCREMENTED|SH3_DMAC_CHCR_TS_8|SH3_DMAC_CHCR_DE_ENABLED|DMAC_CHCR_RL_ACTIVE_LOW);
													// DRAK High, DACK Lo,
													// Source address increase,
													// Transmit size 8bit,
													// DMAC Enable
		READ_REGISTER_ULONG(pDMAOR);				// Reset
		
			WRITE_REGISTER_ULONG(pDMAOR,  SH3_DMAC_DMAOR_DME);	// Run
#endif // (SH_PLATFORM == PLATFORM_ASPEN)

/******************************************************************************
 * End of modification Done by Maneesh Gupta
 *****************************************************************************/

			WRITE_REGISTER_UCHAR(pIMSTCR, (READ_REGISTER_UCHAR(pIMSTCR) & CC_FIR_IMSTCR_RST_BANK) | CC_FIR_IMSTCR_BANK2);// Switch Bank 2
		WRITE_REGISTER_UCHAR(pIIRC3R, CC_FIR_IIRC3R_TMI);	// Timer Interrupt Disabel, clear Interrupt pending flag
		WRITE_REGISTER_UCHAR(pIMSTCR, CC_FIR_IMSTCR_IEN|CC_FIR_IMSTCR_TXEN|CC_FIR_IMSTCR_BANK0);	// FIR, Transmitter Enable
		WRITE_REGISTER_UCHAR(pITC1R,  CC_FIR_ITC1R_RTS|CC_FIR_ITC1R_TFUIEN|CC_FIR_ITC1R_ADRTS| /*CC_FIR_ITC1R_TIDL| */CC_FIR_ITC1R_UA);	
												// RTS,
												// TxFIFO UR/EOM interrupt enable,
												// TxFIFO threshold:Half Empty,
												// EOM auto clear,
												// Tx Idlw control On

	}
	else{
		dwPhysAddressDMARP = (DWORD)CC_FIR_DMARP;
		WRITE_REGISTER_UCHAR(pITMCR,  CC_FIR_ITMCR_TMCR_66);	// CKIO:66MHz
		WRITE_REGISTER_UCHAR(pIMSTCR, (READ_REGISTER_UCHAR(pIMSTCR) & CC_FIR_IMSTCR_RST_BANK)|CC_FIR_IMSTCR_BANK0);
		
		WRITE_REGISTER_UCHAR(pITC1R,   0x00);	//Disable Tx interrupts

		WRITE_REGISTER_UCHAR(pIMISCR, CC_FIR_IMISCR_DCS_RX);	// DMA Channel for Rx
		WRITE_REGISTER_UCHAR(pIRCR,   CC_FIR_IRCR_ACRCC|CC_FIR_IRCR_SCIEN);	// Auto CRC check,Special condition interrupt enable
		WRITE_REGISTER_UCHAR(pIRSTCR, CC_FIR_IRSTCR_RSTC_RXSCI);	// Reset Rx Special Condition Interrupt
		WRITE_REGISTER_UCHAR(pIRSTCR, CC_FIR_IRSTCR_RSTC_RXRFP);	// Reset Rx Ring Frame pointer
		WRITE_REGISTER_UCHAR(pIRSTCR, CC_FIR_IRSTCR_RSTC_RXFIFO);	// Reset Rx FIFO pointer
		WRITE_REGISTER_UCHAR(pIRSTCR, CC_FIR_IRSTCR_RSTC_HUNT);	// Enter Hunt Mode
		WRITE_REGISTER_UCHAR(pIMSTCR, (READ_REGISTER_UCHAR(pIMSTCR) & CC_FIR_IMSTCR_RST_BANK) | CC_FIR_IMSTCR_BANK2);// Switch Bank 2

//		WRITE_REGISTER_UCHAR(pIIRTCR, 0x00);

		WRITE_REGISTER_UCHAR(pIIRC2R, CC_FIR_IIRC2R_CHOP_ENABLE_MAX|CC_FIR_IIRC2R_DSIRI);
									// Autochop Enabled with max tolerance for Error,Disable SIR interrupt
/******************************************************************************
 * Modification Done by Maneesh Gupta
 *
 * According to suggestions given by SH$ h/w Manual,DMA Channel0 is reseted.
 *****************************************************************************/
		WRITE_REGISTER_ULONG(pCHCR0,0);
/******************************************************************************
 * End of modification Done by Maneesh Gupta
 *****************************************************************************/

		WRITE_REGISTER_ULONG(pSAR0, dwPhysAddressDMARP);		// Source address
		WRITE_REGISTER_ULONG(pDAR0, dwPhysAddress);				// Destination address
		WRITE_REGISTER_ULONG(pDMATCR0,DataLength & 0x0000FFFF);	// Transmit byte length
		READ_REGISTER_ULONG(pCHCR0);				// Reset
/******************************************************************************
 * Modification Done by Maneesh Gupta
 *
 * ASPEN/BIGSUR releated definations has been changed for the DMA initialization.
 *****************************************************************************/
#if ((SH_PLATFORM == PLATFORM_ASPEN)||(SH_PLATFORM==PLATFORM_BIGSUR))
		WRITE_REGISTER_ULONG(pCHCR0,  DMAC_CHCR_DS_FALLING_EDGE |DMAC_CHCR_DM_INCREMENTED|DMAC_CHCR_TS_8|DMAC_CHCR_DE_ENABLED);
		//WRITE_REGISTER_ULONG(pCHCR0,  DMAC_CHCR_DS_FALLING_EDGE |DMAC_CHCR_RL_ACTIVE_HIGH|DMAC_CHCR_DM_INCREMENTED|DMAC_CHCR_TS_8|DMAC_CHCR_DE_ENABLED);
													// Distination address increase,
													// Transmit size 8bit,
													// DMAC Enable
		READ_REGISTER_ULONG(pDMAOR);				// Reset
		WRITE_REGISTER_ULONG(pDMAOR,  DMAC_DMAOR_DME);	// Run
//		DEBUGMSG(1,(TEXT("DMAOR=0x%x"),READ_REGISTER_ULONG(pDMAOR)));
#else // (SH_PLATFORM == PLATFORM_ASPEN)
		WRITE_REGISTER_ULONG(pCHCR0,  SH3_DMAC_CHCR_DS_FALLING_EDGE |SH3_DMAC_CHCR_RL_ACTIVE_HIGH|SH3_DMAC_CHCR_DM_INCREMENTED|SH3_DMAC_CHCR_TS_8|SH3_DMAC_CHCR_DE_ENABLED);
													// Distination address increase,
													// Transmit size 8bit,
													// DMAC Enable
		READ_REGISTER_ULONG(pDMAOR);				// Reset
		WRITE_REGISTER_ULONG(pDMAOR,  SH3_DMAC_DMAOR_DME);	// Run
#endif // (SH_PLATFORM == PLATFORM_ASPEN)

/******************************************************************************
 * End of modification Done by Maneesh Gupta
 *****************************************************************************/
		WRITE_REGISTER_UCHAR(pIMSTCR, CC_FIR_IMSTCR_IEN|CC_FIR_IMSTCR_RXEN);	// FIR, Receiver Enable

	}


done:

    DBGDMA((TEXT("-NdisMSetupDmaTransfer [%s]"), DBG_NDIS_RESULT_STR(*pStatus)));
	DEBUGMSG(ZONE_FIRMODE, (TEXT("NdisMSetupDmaTransfer <--\r\n")));
    return;
}

// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
VOID 
NdisMCompleteDmaTransfer(
    PNDIS_STATUS            Status,
    PNDIS_HANDLE            MiniportDmaHandle,
    PNDIS_BUFFER            Buffer,
    ULONG                   Offset,
    ULONG                   Length,
    BOOLEAN                 WriteToDevice
    )
{
	DEBUGMSG(ZONE_FIRMODE, (TEXT("NdisMCompleteDmaTransfer -->\r\n")));
    DBGDMA((TEXT("+NdisMCompleteDmaTransfer %s: buf = 0x%x, offset = %d, len = %d"),
        (WriteToDevice == TRUE) ? TEXT("TX") : TEXT("RX"),
         Buffer, Offset, Length));

    //
    // Disable the DMA
    //


	//Disable DMAC

/******************************************************************************
 * Modification Done by Maneesh Gupta
 *
 * ASPEN/BIGSUR Related bit definations has been changed.
 *****************************************************************************/
#if ((SH_PLATFORM == PLATFORM_ASPEN)||(SH_PLATFORM==PLATFORM_BIGSUR))
    WRITE_REGISTER_ULONG(pCHCR0,READ_REGISTER_ULONG(pCHCR0) & ~DMAC_CHCR_DE_ENABLED);
#else // (SH_PLATFORM == PLATFORM_ASPEN)
    WRITE_REGISTER_ULONG(pCHCR0,READ_REGISTER_ULONG(pCHCR0) & ~SH3_DMAC_CHCR_DE_ENABLED);
#endif // (SH_PLATFORM == PLATFORM_ASPEN)
/******************************************************************************
 * End of modification Done by Maneesh Gupta
 *****************************************************************************/
    WRITE_REGISTER_ULONG(pDMAOR,0x00000000);
    WRITE_REGISTER_UCHAR(pIMSTCR,0x00);

	//SetSirMode();
#ifdef OUTMSG
	RETAILMSG(0,(TEXT("SetSirMode\r\n")));
#endif

    DBGDMA((TEXT("-NdisMCompleteDmaTransfer [NDIS_STATUS_SUCCESS]")));
    *Status = NDIS_STATUS_SUCCESS;
	DEBUGMSG(ZONE_FIRMODE, (TEXT("NdisMCompleteDmaTransfer <--\r\n")));
}



// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------

ULONG 
NdisMReadDmaCounter(
    NDIS_HANDLE             MiniportDmaHandle
    )
{
	ULONG	val;

	DEBUGMSG(ZONE_FIRMODE, (TEXT("NdisMReadDmaCounter <-->\r\n")));
    val = READ_REGISTER_ULONG(pDMATCR0);
    return(val);
}