ndismlib.c

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

/*

  Copyright(c) 1998,1999 SIC/Hitachi,Ltd.

	Module Name:

		ndismlib.c

	Revision History:

		26th May   1999		Released

*/
//#define OUTMSG

#include <windows.h>
#include <ndis.h>
#include "nsc.h"
#include "ndisdma.h"
#include "firregs.h"
/******************************************************************************
 * Modification Done by Maneesh Gupta
 *
 * S1.h has been replaced by platform.h 
 * Mobytel.h has been removed as it is no longer needed.
 * SH4.h has been included.
 *****************************************************************************/
#include "platform.h"
#include "sh4.h"
/******************************************************************************
 * End of modification Done by Maneesh Gupta
 *****************************************************************************/
#include "cc.h"	
#include "settings.h"
#include "oalintr.h"

DWORD dwSysIntrIR=SYSINTR_IR;
DWORD dwSysIntrFirmware=SYSINTR_FIRMWARE;
DWORD dwHD64465Base=HD64465_BASE;


#define FIR_BUFFER_BASE_PA 0x00001000

#define MINIPORT_DMA_HANDLE  (NDIS_HANDLE) 0x45454545

// We will map our virtual address to our dma physical buffer.
// This is used with any buffer that was mapped into our physical
// buffer.

PVOID 
VirtualToPhysAddress(PVOID pvVirtual)
{
	DBGOUT((TEXT("==>VirtualToPhysAddress")));
    // Make sure that the given virtual address is within the range of our buffer.
    ASSERT(((PUCHAR)pvVirtual >= (PUCHAR)g_pvDmaVirtualBase) && 
           ((PUCHAR)pvVirtual < ((PUCHAR)g_pvDmaVirtualBase + NSCIRDA_DMA_BUFFER_LEN)));

	DBGOUT((TEXT("<==VirtualToPhysAddress")));
    // Physical address is the base physical address plus the offset 
    // in the virtual address space.
    return (PVOID)((DWORD)NSCIRDA_DMA_BUFFER_BASE_PA + 
            (DWORD)pvVirtual - (DWORD)g_pvDmaVirtualBase);
}

const int DmaAddrReg[4]  = { 0x00, 0x02, 0x04, 0x06};
const int DmaCountReg[4] = { 0x01, 0x03, 0x05, 0x07};
const int DmaPageReg[4]  = { 0x87, 0x83, 0x81, 0x82};

//
// Define the DMA mode register structure.
//

typedef struct _DMA_MODE
{
    UCHAR Channel : 2;
    UCHAR TransferType : 2;
    UCHAR AutoInitialize : 1;
    UCHAR AddressDecrement : 1;
    UCHAR RequestMode : 2;
}DMA_MODE, *PDMA_MODE;

//
// Define TransferType values.
//

#define VERIFY_TRANSFER     0x00
#define READ_TRANSFER       0x01        // Read from the device.
#define WRITE_TRANSFER      0x02        // Write to the device.

//
// Define RequestMode values.
//

#define DEMAND_REQUEST_MODE         0x00
#define SINGLE_REQUEST_MODE         0x01
#define BLOCK_REQUEST_MODE          0x02
#define CASCADE_REQUEST_MODE        0x03


#define DMA_SETMASK     4
#define DMA_CLEARMASK       0
#define DMA_READ            4  // These two appear backwards, but I think
#define DMA_WRITE           8  // the DMA docs have them mixed up
#define DMA_SINGLE_TRANSFER 0x40
#define DMA_AUTO_INIT       0x10 // Auto initialization mode

//
// Define DMA 1 address and count structure (for 8237 compatibility)
//

typedef struct _DMA1_ADDRESS_COUNT
{
    UCHAR DmaBaseAddress;
    UCHAR DmaBaseCount;
} DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;

//
// Define DMA 1 control register structure (for 8237 compatibility)
//

typedef struct _DMA1_CONTROL
{
    DMA1_ADDRESS_COUNT DmaAddressCount[4];
    UCHAR DmaStatus;
    UCHAR DmaRequest;
    UCHAR SingleMask;
    UCHAR Mode;
    UCHAR ClearBytePointer;
    UCHAR MasterClear;
    UCHAR ClearMask;
    UCHAR AllMask;
} DMA1_CONTROL, *PDMA1_CONTROL;

NDIS_DMA_DESCRIPTION g_DMA_Description;
BOOL                 g_fRegistered;
UINT                 g_nDmaChannel;
//-------------------------------------------------------------------------------
PUCHAR		pBaseAddressDMAC=0;	//  DMA Controller registers
volatile PULONG pSAR0;
volatile PULONG pDAR0;
volatile PULONG pDMATCR0;
volatile PULONG pCHCR0;
volatile PULONG pDMAOR;

void UnMapDmaRegister()
{
	if (pBaseAddressDMAC)
	{
 		VirtualFree(pBaseAddressDMAC, DMAC_REGSIZE, MEM_RELEASE);
    	pBaseAddressDMAC = NULL;
	}
};

BOOL MapDmaRegister()
{
	/*********** DMA Controller Register ***********/
	BOOL nTmpVal;
	DWORD rc;
	if (pBaseAddressDMAC)
		return TRUE;


	pBaseAddressDMAC = VirtualAlloc(0, DMAC_REGSIZE, MEM_RESERVE, PAGE_NOACCESS);
	if(!pBaseAddressDMAC){
		DBGERR((TEXT("VirtualAlloc DMAC reg failed in AllocateFirRegs()!")));
		return (FALSE);
	}
	else{
		nTmpVal = VirtualCopy((PVOID)pBaseAddressDMAC,(PVOID)DMAC_REGBASE,
								DMAC_REGSIZE, PAGE_READWRITE | PAGE_NOCACHE);
		if (nTmpVal != TRUE){
			rc = GetLastError(); 
			DBGERR((TEXT("VirtualCopy DMAC reg failed in AllocateFirRegs()! Return Code:%x"),rc));
			return (FALSE);
		}
	}

#if ((SH_PLATFORM == PLATFORM_ASPEN)||(SH_PLATFORM == PLATFORM_BIGSUR))
	pSAR0 = (PULONG)((PVBYTE)pBaseAddressDMAC + DMAC_SAR0_OFFSET);
	pDAR0 = (PULONG)((PVBYTE)pBaseAddressDMAC + DMAC_DAR0_OFFSET);
	pDMATCR0 = (PULONG)((PVBYTE)pBaseAddressDMAC + DMAC_DMATCR0_OFFSET);
	pCHCR0 = (PULONG)((PVBYTE)pBaseAddressDMAC + DMAC_CHCR0_OFFSET);
	pDMAOR = (PULONG)((PVBYTE)pBaseAddressDMAC + DMAC_DMAOR_OFFSET);
#else (SH_PLATFORM == PLATFORM_ASPEN)
	pSAR0 = (PULONG)((PVBYTE)pBaseAddressDMAC + DMAC_SAR0_OFFSET);
	pDAR0 = (PULONG)((PVBYTE)pBaseAddressDMAC + DMAC_DAR0_OFFSET);
	pDMATCR0 = (PULONG)((PVBYTE)pBaseAddressDMAC + DMAC_DMATCR0_OFFSET);
	pCHCR0 = (PULONG)((PVBYTE)pBaseAddressDMAC + DMAC_CHCR0_OFFSET);
	pDMAOR = (PULONG)((PVBYTE)pBaseAddressDMAC + DMAC_DMAOR_OFFSET);
#endif (SH_PLATFORM == PLATFORM_ASPEN)
	return TRUE;

}
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
NDIS_STATUS 
NdisMRegisterDmaChannel(
    PNDIS_HANDLE            phMiniportDmaHandle,
    NDIS_HANDLE             hMiniportAdapterHandle,
    UINT                    nDmaChannel,
    BOOLEAN                 fDma32BitAddresses,
    PNDIS_DMA_DESCRIPTION   pDmaDescription,
    ULONG                   ulMaximumLength
    )
{
    NDIS_STATUS Status = NDIS_STATUS_SUCCESS;

	DBGOUT((TEXT("==>NdisMRegisterDmaChannel")));
    DEBUGMSG(ZONE_INIT | ZONE_DMA,
        (TEXT("+NdisMRegisterDmaChannel(%#x, %#x, %d, %d, %#x, %d\r\n"),
         phMiniportDmaHandle,
         hMiniportAdapterHandle,
         nDmaChannel, 
         fDma32BitAddresses,
         pDmaDescription,
         ulMaximumLength));
    
    //
    // Check to make sure we're not already registered. Only allow one at a time.
    //

    if (g_fRegistered)
    {
        Status = NDIS_STATUS_RESOURCE_CONFLICT;
        goto done;
    }

    //
    // One DMA Channel per driver. Return Constant.
    //

    *phMiniportDmaHandle = MINIPORT_DMA_HANDLE;

    //
    // Store the description for later use.
    //

    memcpy(&g_DMA_Description, pDmaDescription, sizeof(NDIS_DMA_DESCRIPTION));
    g_nDmaChannel = nDmaChannel;

    if (g_nDmaChannel > 3)
    {
        DBGERR((TEXT("Whoa! The channel is > 3. Not available in this sample driver!")));
        Status = NDIS_STATUS_RESOURCES;
        goto done;
    }

    //
    // Indicate that we are registered.
    //

    g_fRegistered = TRUE;

done:

    DEBUGMSG(ZONE_INIT | ZONE_DMA,
        (TEXT("-NdisMRegisterDmaChannel [%s, hDma = %#x]\r\n"), 
         DBG_NDIS_RESULT_STR(Status), *phMiniportDmaHandle));

	DBGOUT((TEXT("<==NdisMRegisterDmaChannel")));
    return (Status);
}

// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
VOID 
NdisMDeregisterDmaChannel(
    PNDIS_HANDLE            phMiniportDmaHandle
    )
{
	DBGOUT((TEXT("==>NdisMDeregisterDmaChannel")));
    DEBUGMSG(ZONE_INIT | ZONE_DMA,
        (TEXT("+NdisMDeregisterDmaChannel(%#x)\r\n"), phMiniportDmaHandle));
    
    if (*phMiniportDmaHandle == MINIPORT_DMA_HANDLE)
    {
        g_fRegistered = FALSE;
    }

    DEBUGMSG(ZONE_INIT | ZONE_DMA, (TEXT("-NdisMDeregisterDmaChannel\r\n")));