vrc5074.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 321 行

/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995-1998  Microsoft Corporation

Module Name:

   Vrc5074.h

Abstract:

    Register and constant definitions for Vrc5074 memory controller chip

Notes:


--*/


#ifndef _VRC5074_H_
#define _VRC5074_H_

#define VRC5074_PCIVID              0x009B1033

//
// PDAR registers/fields
//

#define NILE4_SDRAM0                0x0000
#define NILE4_SDRAM1                0x0008
#define NILE4_DCS2                  0x0010
#define NILE4_DCS3                  0x0018
#define NILE4_DCS4                  0x0020
#define NILE4_DCS5                  0x0028
#define NILE4_DCS6                  0x0030
#define NILE4_DCS7                  0x0038
#define NILE4_DCS8                  0x0040
#define NILE4_PCIW0                 0x0060
#define NILE4_PCIW1                 0x0068
#define NILE4_INTCS                 0x0070
#define NILE4_BOOTCS                0x0078

#define NILE4_DSCFN                 0x0150

#define PDAR_4GB                    0x4
#define PDAR_2GB                    0x5
#define PDAR_1GB                    0x6
#define PDAR_512MB                  0x7
#define PDAR_256MB                  0x8
#define PDAR_128MB                  0x9
#define PDAR_64MB                   0xA
#define PDAR_32MB                   0xB
#define PDAR_16MB                   0xC
#define PDAR_8MB                    0xD
#define PDAR_4MB                    0xE
#define PDAR_2MB                    0xF

#define PDAR_MEMLOC                 (1<<4)
#define PDAR_VISPCI                 (1<<5)
#define PDAR_8BITS                  (0<<6)
#define PDAR_16BITS                 (1<<6)
#define PDAR_32BITS                 (2<<6)
#define PDAR_64BITS                 (3<<6)

/* CPU Interface Control Registers */

#define NILE4_CPUSTAT               0x0080
#define NILE4_INTCTRL               0x0088
 
#define NILE4_INTSTAT0              0x0090 
#define NILE4_INTSTAT1              0x0098
#define NILE4_INTCLR                0x00a0
#define NILE4_INTPPES               0x00a8

/* Main Memory Control Registers */

#define NILE4_MEMCTRL               0x00c0
#define NILE4_ACSTIME               0x00c8
#define NILE4_CHKERR                0x00d0

/* PCI Control Registers */

#define NILE4_PCICTRL               0x00e0
#define NILE4_PCIARB                0x00e8
#define NILE4_PCIINIT0              0x00f0
#define NILE4_PCIINIT1              0x00f8
#define NILE4_PCIERR                0x00b8

#define PCIINIT_ACCESS_32           (0x1<<4)
#define PCIINIT_CONFIGTYPE0         (0x0<<9)
#define PCIINIT_CONFIGTYPE1         (0x1<<9)
#define PCIINIT_TYPE_MEM            (0x6<<0)
#define PCIINIT_TYPE_IO             (0x2<<0)
#define PCIINIT_TYPE_CONFIG         (0xA<<0)
#define PCIINIT_TYPE_INTACK         (0x0<<0)

/* DMA Control Registers */

#define NILE4_DMACTRL0              0x0180
#define NILE4_DMASRCA0              0x0188
#define NILE4_DMADESA0              0x0190
#define NILE4_DMACTRL1              0x0198
#define NILE4_DMASRCA1              0x01a0
#define NILE4_DMADESA1              0x01a8

/* TIMER CONROL REGISTERS */

#define NILE4_T0CTRL                0x01c0
#define NILE4_T0CNTR                0x01c8
#define NILE4_T1CTRL                0x01d0
#define NILE4_T1CNTR                0x01d8
#define NILE4_T2CTRL                0x01e0
#define NILE4_T2CNTR                0x01e8
#define NILE4_T3CTRL                0x01f0
#define NILE4_T3CNTR                0x01f8

/* UART REGISTERS */

#define UART0_BASE                  0xbfa00300 /* nile4 com port */
/*#define UART0_BASE                0xa60003f8 */ /*m1543 com1 port */
#define NILE4_UARTRBR               0x0300
#define NILE4_UARTTHR               0x0300
#define NILE4_UARTIER               0x0308
#define NILE4_UARTDLL               0x0300
#define NILE4_UARTDLM               0x0308
#define NILE4_UARTIIR               0x0310
#define NILE4_UARTFCR               0x0310
#define NILE4_UARTLCR               0x0318
#define NILE4_UARTMCR               0x0320
#define NILE4_UARTLSR               0x0328
#define NILE4_UARTMSR               0x0330
#define NILE4_UARTSCR               0x0338

/* PCI CONFIG SPACE OF NILE4*/

#define NILE4_PCIVID                0x200
#define NILE4_PCICMD                0x204
#define NILE4_PCIREVID              0x208
#define NILE4_PCICLSIZ              0x20C
#define NILE4_BARC                  0x210 
#define NILE4_BAR0                  0x218
#define NILE4_BAR1                  0x220
#define NILE4_BAR2                  0x240
#define NILE4_BAR3                  0x248
#define NILE4_BAR4                  0x250
#define NILE4_BAR5                  0x258
#define NILE4_BAR6                  0x260
#define NILE4_BAR7                  0x268
#define NILE4_BAR8                  0x270
#define NILE4_BARB                  0x278

#ifndef ASSEMBLY_LANGUAGE

//
// register structure
//

typedef struct {
    union {
        volatile ULONG Low;
        volatile ULONG Lo;
    };
    union {
        volatile ULONG High;
        volatile ULONG Hi;
    };
} VRC5074_REG, *PVRC5074_REG;

typedef struct {
    union {
        UCHAR PDAR_Space[0x80];
        struct {
            VRC5074_REG SDRAM0;
            VRC5074_REG SDRAM1;
            VRC5074_REG DCS2;
            VRC5074_REG DCS3;
            VRC5074_REG DCS4;
            VRC5074_REG DCS5;
            VRC5074_REG DCS6;
            VRC5074_REG DCS7;
            VRC5074_REG DCS8;
            VRC5074_REG RFU9;
            VRC5074_REG RFUA;
            VRC5074_REG RFUB;
            VRC5074_REG PCIW0;
            VRC5074_REG PCIW1;
            VRC5074_REG INTCS;
            VRC5074_REG BOOTCS;
        };
    };

    union {
        UCHAR CPU_Registers[0xC0-0x80];
        struct {
            VRC5074_REG CPUSTAT;
            VRC5074_REG INTCTRL;
            VRC5074_REG INTSTAT0;
            VRC5074_REG INTSTAT1;
            VRC5074_REG INTCLR;
            VRC5074_REG INTPPES;
            VRC5074_REG RESERVED_0B0;
            VRC5074_REG PCIERR;
        };
    };

    union {
        UCHAR Memory_Registers[0xE0-0xC0];
        struct {
            VRC5074_REG MEMCTRL;
            VRC5074_REG ACSTIME;
            VRC5074_REG CHKERR;
        };
    };

    union {
        UCHAR PCIBus_Registers[0x100-0xE0];
        struct {
            VRC5074_REG PCICTRL;
            VRC5074_REG PCIARB;
            VRC5074_REG PCIINIT0;
            VRC5074_REG PCIINIT1;
        };
    };

    union {
        UCHAR LocalBus_Registers[0x180-0x100];
        struct {
            VRC5074_REG LCNFG;
            VRC5074_REG RESERVED_108;
            VRC5074_REG LCST2;
            VRC5074_REG LCST3;
            VRC5074_REG LCST4;
            VRC5074_REG LCST5;
            VRC5074_REG LCST6;
            VRC5074_REG LCST7;
            VRC5074_REG LCST8;
            VRC5074_REG RESERVED_148;
            VRC5074_REG DCSFN;
            VRC5074_REG DCSIO;
            VRC5074_REG RESERVED_160;
            VRC5074_REG RESERVED_168;
            VRC5074_REG RESERVED_170;
            VRC5074_REG BCST;
        };
    };

    union {
        UCHAR Dma_Registers[0x1C0-0x180];
        struct {
            VRC5074_REG DMACTRL0;
            VRC5074_REG DMASRCA0;
            VRC5074_REG DMADESA0;
            VRC5074_REG DMACTRL1;
            VRC5074_REG DMASRCA1;
            VRC5074_REG DMADESA1;
        };
    };

    union {
        UCHAR Timer_Registers[0x200-0x180];
        struct {
            VRC5074_REG T0CTRL;
            VRC5074_REG T0CNTR;
            VRC5074_REG T1CTRL;
            VRC5074_REG T1CNTR;
            VRC5074_REG T2CTRL;
            VRC5074_REG T2CNTR;
            VRC5074_REG T3CTRL;
            VRC5074_REG T3CNTR;
        };
    };

    union {
        UCHAR PCIConfig_Registers[0x300-0x200];
        struct {
            ULONG VID;
            ULONG PCICMD;
            ULONG REVID;
            ULONG CLSIZ;
            VRC5074_REG BARC;
            VRC5074_REG BAR0;
            VRC5074_REG BAR1;
            VRC5074_REG RESERVED_228;
            ULONG RESERVED_230;
            ULONG INTLIN;
            VRC5074_REG BAR2;
            VRC5074_REG BAR3;
            VRC5074_REG BAR4;
            VRC5074_REG BAR5;
            VRC5074_REG BAR6;
            VRC5074_REG BAR7;
            VRC5074_REG BAR8;
            VRC5074_REG BARB;
        };
    };

    union {
        struct {
            VRC5074_REG UARTRBR;
            VRC5074_REG UARTTHR;
            VRC5074_REG UARTIER;
            VRC5074_REG UARTDLL;
            VRC5074_REG UARTDLM;
            VRC5074_REG UARTIIR;
            VRC5074_REG UARTFCR;
            VRC5074_REG UARTLCR;
            VRC5074_REG UARTMCR;
            VRC5074_REG UARTLSR;
            VRC5074_REG UARTMSR;
            VRC5074_REG UARTSCR;
        };
    };

} VRC5074_CONTROL, *PVRC5074_CONTROL;

#endif

#endif //_VRC5074_H_