phx2dinf.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 227 行

//
//  Filename: phx2dinf.h 
//  $Revision: 2 $
//
//  Description: Defines 2D info used fro 3D initialization
//
//  Trade secret of ATI Technologies, Inc.
//  Copyright 1995, ATI Technologies, Inc., (unpublished) 
//  
//  All rights reserved.  This notice is intended as a precaution against
//  inadvertent publication and does not imply publication or any waiver
//  of confidentiality.  The year included in the foregoing notice is the
//  year of creation of the work.
//  
//  

#ifndef ATI_PHX2DINF_H
#define ATI_PHX2DINF_H

//
// Handle private interface between the 3D driver and the 2D GDI 
// driver
//

//
//  private Windows 95 GDI drive escape that retrieves specific
//  HW info used for 3D driver initialization
//
#define CTRL_GET_HW_INFO        0x73F0
#define CTRL_LOCK_FRAMEBUFFER   0x73F1
#define CTRL_UNLOCK_FRAMEBUFFER 0x73F2

#define CTRL_GAMMA_SET          0x7392
#define CTRL_GAMMA_GET          0x7393
//
//      note these proprocessor macros are defined as follows: the upper 
//      byte of the lower word is used for major chip revs, and the lower
//      byte is used for minor revisions (metal fixes ...).      The upper word
//      of the dwAsicID member is currently undefined and should be 0.
//
//   There is no such thing as a LTG2!
#define CHIPID_NOTGT                            0
#define CHIPID_GTA1                             0x0101
#define CHIPID_GTA2                             0x0102
#define CHIPID_GTB1                             0x0201
#define CHIPID_GTB1S2                           0x0202
#define CHIPID_GTB1U1                           0x0203
#define CHIPID_GTB1U2                           0x0204
#define CHIPID_GTB1U3                           0x0205
#define CHIPID_LTG1                             0x0301
#define CHIPID_LTG3                             0x0303  // IanB 4/30/97
#define CHIPID_RAGE3_1                          0x0401  // Rage3 A1
#define CHIPID_RAGE3_2                          0x0402  // Rage3 A2 (metal spin)
#define CHIPID_RAGE3_3                          0x0403  // Reserved, never used
#define CHIPID_RAGE3_4                          0x0404  // Rage3 A3 
#define CHIPID_RAGE3_5                          0x0405
#define CHIPID_NOTYET							0x9000  // chrisb 3/31/97

//for chip class
#define CHIPCLASS_GTA                   0x0100
#define CHIPCLASS_GTB                   0x0200
#define CHIPCLASS_UMC                   0x1200
#define CHIPCLASS_LTG                   0x0300
#define CHIPCLASS_RAGE3                 0x0400

// As this struct grows, we need to be able to make decisions based on 
// the size of the struct experienced in the field, to ensure compatibility
// between old and new revs of 2D and 3D drivers. New features should only be
// enabled when both 2D and 3D drivers are knowledgable of that feature as
// manifested in the size of the struct seen and expected  The following
// defines are provided for comparing size against new functions.

#define PHX2DHWINFO_SIZE_ORIG         52
#define PHX2DHWINFO_SIZE_WITH_MASKS   68
#define PHX2DHWINFO_SIZE_WITH_P6WC    72
#define PHX2DHWINFO_SIZE_WITH_RAGE3   84

// Use of dwRegisterWCBase field (philr 9/9/96)
// -----------------------------
// The dwRegisterWCBase field has been added to allow use of a WC or
// Write Combining aperture on P6 and other processors which provide
// a high performance WC register aperture that is weakly ordered.
// Whoever fills out the PHX2DHWINFO struct should set dwRegisterBaseAddr
// to the UC (Uncached) register aperture and dwRegisterWCBase to the 
// WC (Write Combining) aperture. If we are running on a CPU without a
// WC aperture (eg pre-P6), then the dwRegisterWCBase field should be set
// to the UC aperture (same as dwRegisterBaseAddr).

typedef struct {
    DWORD   dwSize;                 // size of this struct
    DWORD   dwVideoBaseAddr;        // linear address to aperture
    DWORD   dwOffScreenAddr;        // linear address to offscreen memory
    DWORD   dwOffScreenSize;        // size of offscreen memory
    DWORD   dwTotalRAM;             // amount of RAM on the card
    DWORD   dwFIFOSize;             // size of FIFO
    DWORD   dwScreenWidth;          // screen width
    DWORD   dwScreenHeight;         // screen height
    DWORD   dwScreenPitch;          // screen pitch
    DWORD   dwBpp;                  // bits per pixel
				    //   1
				    //   4
				    //   8
				    //  15 = 1555 format
				    //  16 = 565  format
				    //  24
				    //  32
    BOOL    b3DAvail;               // driver supports 3D operations
    DWORD   dwChipID;               // 3D chip id code
    DWORD   dwChipRevision;         // 3D chip revision
    
	DWORD   dwAlphaBitMask;         // Alpha bit mask
	DWORD   dwRedBitMask;           // Red Bit Mask
	DWORD   dwGreenBitMask;         // Green Bit Mask
	DWORD   dwBlueBitMask;          // Blue Bit Mask
    
    DWORD   dwAGPBaseAddr;          // Base of AGP linear address space 
    DWORD   dwAGPMemSize ;          // Size in bytes of AGP memory 

    DWORD   dwOffScreenPaletteAddr; // linear address to frame buffer area
                                    // for texture palette source, 
                                    // for Rage3_2 (metal spin), it is the offset
    DWORD   dwOffScreenPaletteSize; // Size in bytes of texture palette area

} PHX2DHWINFO, *PPHX2DHWINFO, FAR *FPPHX2DHWINFO;

#ifdef RCS_H_KEYS
    static char *rcsid_h_phx2dinf_ati = "$Revision: 2 $" __FILE__;
#endif

#endif // ATI_PHX2DINF_H

//
// $Author: Markv $
// $Revision: 2 $
// $Date: 10/16/98 1:20p $
// $Modtime: 10/16/98 12:45p $
// $Log: /Scorpion/WinceHAP/PLATFORM/CEPC/Drivers/Common/phx2dinf.h $
// 
// 2     10/16/98 1:20p Markv
// 
// 1     10/07/98 12:05p Markv
// 
// 1     2/20/98 12:13p Davidg
// Common driver files
// 
// 1     12/17/97 10:28p Ssatnick
// Basic GDI Rage Pro display driver implementation
// 
//    Rev 2.25   02 Jun 1997 15:18:24   xwu
// added comments on chipid for rage3 series
// 
//    Rev 2.24   30 Apr 1997 16:16:22   ianb
// Added CHIPID_LTG3 define.
// 
//    Rev 2.23   22 Apr 1997 14:23:12   ianb
//  Added two #defines related to Jimmy A.'s fix in bpalette.cpp
// 
//    Rev 2.22   05 Apr 1997 18:07:30   xwu
// modified the comments for dwOffScreenPaletteAddr.
// 
//    Rev 2.21   Apr 02 1997 15:20:28   mmintz
// added chip class reference
// 
//    Rev 2.20   31 Mar 1997 13:46:12   chrisb
// added CHIPID_NOTYET to flag disabled changes
// 
//    Rev 2.19   07 Mar 1997 10:40:20   davidg
// added definitions for rage3 revs 2 through5
// 
//    Rev 2.18   Feb 10 1997 12:22:26   philr
// added fields to PHX2DHWINFO struct for Rage 3.
// 
//    Rev 2.17   Jan 29 1997 13:29:12   philr
// added chipid for GT-B1U3
// 
//    Rev 2.16   Jan 23 1997 15:40:16   mmintz
// added rage 3 define
// 
//    Rev 2.15   Jan 08 1997 08:51:54   mmintz
// added LTG support
// 
//    Rev 2.14   Oct 29 1996 18:59:22   philr
// added chip ID for GTB1U2
// 
//    Rev 2.13   Oct 07 1996 11:17:18   philr
// added support for P6 WC aperture
// 
//    Rev 2.12   Aug 28 1996 17:11:22   cjiang
// Restore the development tree since the changes made between
// Aug. 15 and Aug 23 are lost on the server but exist on
// my machine. 
// 
//    Rev 2.11   Aug 15 1996 11:37:40   philr
// added CHIPID_GTB1U1 to list of known chips
// 
//    Rev 2.10   Jul 23 1996 13:12:44   mmintz
// added chip id for S1 rev of GT-B
// 
//    Rev 2.9   May 20 1996 12:41:18   paulc
// fxied type in chip revision macros
// 
//    Rev 2.8   May 20 1996 12:40:26   paulc
// No change.
// 
//    Rev 2.7   May 20 1996 11:39:42   paulc
// updated preoprocessor macros for better id and expansion
// 
//    Rev 2.6   May 20 1996 11:30:04   paulc
// added preoprocessor defines for dwChipID
// 
//    Rev 2.5   Jan 17 1996 13:33:00   paulc
// added bit masks for RGBA 
// 
//    Rev 2.4   Nov 04 1995 18:09:48   paulc
// added additional fields to the 2d inf struct to accomodate 
// asic rev and 3d caps bit (btw this is really tomp)
// 
//    Rev 2.3   Nov 02 1995 20:48:10   paulc
// added drive escape to lock/unlock frame buffer access from gdi
// 
//    Rev 2.2   Nov 02 1995 17:23:40   paulc
// added new drive escape for cleaning up after 3D operations
// 
//    Rev 2.1   Oct 29 1995 15:13:32   paulc
// Initial revision.
//