alt_def.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 121 行

/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995-1998  Microsoft Corporation

Module Name:

   alt_def.h

Abstract:

    This module is the header file that describes hardware addresses
    for the altoona reference platform.

Notes:


--*/


#ifndef _ALTOONA_DEF_H_
#define _ALTOONA_DEF_H_

// define below for new 5476 card  ....sudhakar

#define NEW5476
//
// taken from ksmips.h
//

#define KUSEG_BASE 0x0
#define KSEG0_BASE 0x80000000
#define KSEG1_BASE 0xa0000000
#define KSEG2_BASE 0xc0000000

//
// Memory map for ALTOONA as defined by Solo chip set
//

#define MEMORY_BASE          0x00000000
#define PCI_MEMORY_BASE      0x20000000
#define PCI_CONFIG_BASE      0x18000000
#define PCI_IO_BASE          0x18000000
#define PCI_INTACK_BASE      0x18000000
#define FLASH_BASE           0x04000000   //sudhakar 1fc00000
#define FLASH_BASE1          0x05000000   //sudhakar 1fc00000
#define BOOT_BASE            0x05c00000  //sudhakar
#define FLASH_ETHER_BASE     0x05c40000  //sudhakar
#define VRC5074_BASE         0x1FA00000
#define PROM_BASE            0x1FC00000
#define CONTROL_REG_BASE     0x14000000 //sudhakar

#define DIP_SWITCH_BASE      0x13000000  //sudhakar
#define LED_BASE             (PCI_IO_BASE + 0x80)
#define NVRAM_BASE           (PCI_MEMORY_BASE + 0x00)
#define UART1_BASE           (PCI_IO_BASE + 0x3F8)
#define UART2_BASE           (PCI_IO_BASE +0x2F8)
#define VRC5074UART_BASE     (VRC5074_BASE + 0x300)
#define PARALLEL_BASE        (PCI_IO_BASE + 0x378)
#define CONFIGPORT_BASE      (PCI_IO_BASE + 0x3F0)
#define FLOPPY_BASE          (PCI_IO_BASE + 0x3E0)

//#define MONITOR_BASE_ADDRESS 0x83fc0000
#define MONITOR_BASE_ADDRESS 0x83000000
#define MONITOR_SIZE         0x00040000  
#define MONITOR_STACK_SIZE   0x00008000
#define DRAM_SIZE            0x01000000
#define PCI_MEMORY_SIZE      PCI_IO_BASE - PCI_MEMORY_BASE
#define PCI_CONFIG_SIZE      0x04000000

#define UncachedBaseOfRAM() (KSEG1_BASE + MEMORY_BASE)
#define CachedBaseOfRAM()   (KSEG0_BASE + MEMORY_BASE)

/*
** PROM entry point definitions
**
** Define base address of prom entry vector and prom entry macro.
*/

#define PROM_ENTRY(x) (PROM_BASE + ((x-1) * 8))

//
// PCI IDSEL configurations
//
#ifdef  NEW5476
#define IDSEL_SLOT1        16
#define IDSEL_SLOT2        19
#define IDSEL_SLOT3        20
#else
#define IDSEL_SLOT1        20
#define IDSEL_SLOT2        21
#define IDSEL_SLOT3        22
#endif
#define IDSEL_VRC5074      23

#ifdef NEW5476
#define IDSEL_DEC21140A    17
#else
#define IDSEL_DEC21140A    19
#endif
#define IDSEL_ENET         IDSEL_DEC21140A
#define IDSEL_M1543        18
#define IDSEL_ISABRIDGE    IDSEL_M1543
#define IDSEL_IDE          24
#define IDSEL_PMU          14
#define IDSEL_USB          13

//
// Boot Flags (coupled with hal.h)
//

#define BF_KITTANNING     1
#define BF_COLDBOOT         0
#define BF_WARMPOWEROFF  0x40
#define BF_REFLASHIMAGE  0x80
#define BF_BOOTBROWSER   0x100

#endif /* _ALTOONA_DEF_H_ */