oalintr.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 107 行

/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995-1998  Microsoft Corporation

Module Name:

   oalintr.h

Abstract:

Author:


Notes:

--*/


#ifndef _oalintr_h_
#define _oalintr_h_


/////////////////////////////////////////////////////////////////////////////
//
// Interrupt source ID for Boston platform
//

#define ISAINTR_VECTOR        0    // ISA interrupt vector base.

#define ALNINTR_IRQ0          0    /* ISA IRQ 0 */
#define ALNINTR_IRQ1          1    /* ISA IRQ 1 */
#define ALNINTR_IRQ2          2    /* ISA IRQ 2 */
#define ALNINTR_IRQ3          3    /* ISA IRQ 3 */
#define ALNINTR_IRQ4          4    /* ISA IRQ 4 */
#define ALNINTR_IRQ5          5    /* ISA IRQ 5 */
#define ALNINTR_IRQ6          6    /* ISA IRQ 6 */
#define ALNINTR_IRQ7          7    /* ISA IRQ 7 */
#define ALNINTR_IRQ8          8    /* ISA IRQ 8 */
#define ALNINTR_IRQ9          9    /* ISA IRQ 9 */
#define ALNINTR_IRQ10         10   /* ISA IRQ 10 */
#define ALNINTR_IRQ11         11   /* ISA IRQ 11 */
#define ALNINTR_IRQ12         12   /* ISA IRQ 12 */
#define ALNINTR_IRQ13         13   /* ISA IRQ 13 */
#define ALNINTR_IRQ14         14   /* ISA IRQ 14 */
#define ALNINTR_IRQ15         15   /* ISA IRQ 15 */



#define MASTERINTR_VECTOR     16   // PCI master interrupt vector base.

#define ALNINTR_CPU_PERR      16   /* CPU parity check error interrupt*/
#define ALNINTR_CPU_NOTARGET  17   /* CPU no target error decode interrupt */
#define ALNINTR_MERR          18   /* Memory check error interrupt */
#define ALNINTR_DMA           19   /* Build in DMA controller interrupt */
#define ALNINTR_UART          20   /* Build in UART interrupt */
#define ALNINTR_WATCHDOG      21   /* Build in watch dog timer interrupt */
#define ALNINTR_TIMER         22   /* Build in gerneral purpose timer int */
#define ALNINTR_BUS_TIMEOUT   23   /* Local bus read timeout interrupt */
#define ALNINTR_PCI_INTA      24   /* PCI INTA */
#define ALNINTR_PCI_INTB      25   /* PCI INTB */
#define ALNINTR_PCI_INTC      26   /* PCI INTC */
#define ALNINTR_PCI_INTD      27   /* PCI INTD */
#define ALNINTR_PCI_INTE      28   /* PCI INTE */
#define ALNINTR_RESERVE0      29
#define ALNINTR_PCI_SERR      30   /* PCI SERR */
#define ALNINTR_PCI_ERR       31   /* PCI internal error */

#define ALNINTR_MAX           31   // Max interrupt vector.
#define ALNINTR_NULL          255  // Bogus interrupt vector (initializer).

//
/////////////////////////////////////////////////////////////////////////////


/////////////////////////////////////////////////////////////////////////////
//
// SYSINTR values
//

#define SYSINTR_KEYBOARD        (SYSINTR_FIRMWARE+0)
#define SYSINTR_MOUSE           (SYSINTR_FIRMWARE+1)
#define SYSINTR_SERIAL1         (SYSINTR_FIRMWARE+2)
#define SYSINTR_SERIAL2         (SYSINTR_FIRMWARE+3)
#define SYSINTR_PARALLEL        (SYSINTR_FIRMWARE+4)
#define SYSINTR_IDE             (SYSINTR_FIRMWARE+5)
#define SYSINTR_USB             (SYSINTR_FIRMWARE+6)
#define SYSINTR_IR              (SYSINTR_FIRMWARE+7)
#define SYSINTR_AUDIO           (SYSINTR_FIRMWARE+8)
#define SYSINTR_ETHER           (SYSINTR_FIRMWARE+9)
#define SYSINTR_VIDEO           (SYSINTR_FIRMWARE+10)
#define SYSINTR_GEN_SLOT3       (SYSINTR_FIRMWARE+11)
#define SYSINTR_GEN_SLOT4       (SYSINTR_FIRMWARE+12)

#define SYSINTR_ISA_GROUP       (SYSINTR_FIRMWARE+13)  // 1543 ISA interrupts.
                                                       // This reps some of the
                                                       // ints above.
#define SYSINTR_MAX             (SYSINTR_FIRMWARE+13)

//
/////////////////////////////////////////////////////////////////////////////

#endif /* End of _oalintr_h_ */