hal.h

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 182 行

/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995-1998  Microsoft Corporation

Module Name:

   hal.h

Abstract:

   Defines for Altoona platform used only by HAL

Author:

   Jun Liu (junliu) 22-June-98

Notes:


--*/

#ifndef _hal_h_
#define _hal_h_

#include <vrc5074.h>


#ifndef CESH_BAUD
#define CESH_BAUD                  38400
#endif

#ifndef DEBUGGER_BAUD
#define DEBUGGER_BAUD              38400
#endif

#define pVRC5074 ((PVRC5074_CONTROL)(VRC5074_BASE | KSEG1_BASE))

void InitClock(void);
int  OEMParallelPortInit(void);

VOID InitBusInfo();
VOID PCIInitBusInfo();
VOID ISAInitBusInfo();
VOID InitInterrupts();
VOID InitPICs();
VOID SYSDoneInterrupt(UCHAR ucInterrupt);
VOID SYSEnableInterrupt(UCHAR ucInterrupt, BOOL bEnabled);
VOID PICEnableInterrupt(UCHAR ucInterrupt, BOOL bEnabled);
BOOL OEMEnableSerialBuffer(PKERNEL_SERIAL_INFO pSerialInfo,PKERNEL_SERIAL_INFO *ppKernelSerialInfo);
BOOL OEMDisableSerialBuffer(DWORD dwIntID);


int InitIGSInfo();
VOID IGSEnableInterrupt(DWORD dwVector, BOOL bEnable);



ULONG ISAGetBusDataByOffset
(
    IN ULONG BusNumber,
    IN ULONG SlotNumber,
    IN PVOID Buffer,
    IN ULONG Offset,
    IN ULONG Length
);


ULONG ISASetBusDataByOffset
(
    IN ULONG BusNumber,
    IN ULONG SlotNumber,
    IN PVOID Buffer,
    IN ULONG Offset,
    IN ULONG Length
);


ULONG PCIGetBusDataByOffset
(
    IN ULONG BusNumber,
    IN ULONG SlotNumber,
    IN PVOID Buffer,
    IN ULONG Offset,
    IN ULONG Length
);


ULONG PCISetBusDataByOffset
(
    IN ULONG BusNumber,
    IN ULONG SlotNumber,
    IN PVOID Buffer,
    IN ULONG Offset,
    IN ULONG Length
);



/*
** Interrupt ID arrays
*/
extern UCHAR IMAP_Sys2Aln[SYSINTR_MAX];
extern UCHAR IMAP_Aln2Sys[ALNINTR_MAX];


/*
** CPU Interrupt levels
*/
#define INT_LEVEL0       0
#define INT_LEVEL1       1
#define INT_LEVEL2       2
#define INT_LEVEL3       3
#define INT_LEVEL4       4
#define INT_LEVEL5       5
#define INT_LEVEL_NMI    6


/*
** INTCTRL register bits
*/
#define INTCTRLL_CPCEPRI      0    /* CPU parity check error (even parity) interrupt priority*/
#define INTCTRLL_CPCEEN       3    /* CPU parity check error (even parity) interrupt enable*/
#define INTCTRLL_CNTDPRTI     4    /* CPU no target error decode interrupt priority */
#define INTCTRLL_CNTDEN       7    /* CPU no target error decode interrupt enable*/
#define INTCTRLL_MCEPRI       8    /* Memory check error interrupt priority*/
#define INTCTRLL_MCEEN        11   /* Memory check error interrupt enable*/
#define INTCTRLL_DMAPRI       12   /* Build in DMA controller interrupt priority*/
#define INTCTRLL_DMAEN        15   /* Build in DMA controller interrupt enable*/
#define INTCTRLL_UARTPRI      16   /* Build in UART interrupt priority*/
#define INTCTRLL_UARTEN       19   /* Build in UART interrupt enable*/
#define INTCTRLL_WDOGPRI      20   /* Build in watch dog timer interrupt priority*/
#define INTCTRLL_WDOGEN       23   /* Build in watch dog timer interrupt enable*/
#define INTCTRLL_GPTPRI       24   /* Build in gerneral purpose timer interrupt priority*/
#define INTCTRLL_GPTEN        27   /* Build in gerneral purpose timer interrupt enable*/
#define INTCTRLL_LBRTDPRI     38   /* Local bus read timeout interrupt priority*/
#define INTCTRLL_LBRTDEN      31   /* Local bus read timeout interrupt enable*/
#define INTCTRLH_INTAPRI      0    /* PCI INTA priority*/
#define INTCTRLH_INTAEN       3    /* PCI INTA enable*/
#define INTCTRLH_INTBPRI      4    /* PCI INTB priority*/
#define INTCTRLH_INTBEN       7    /* PCI INTB enable*/
#define INTCTRLH_INTCPRI      8    /* PCI INTC priority*/
#define INTCTRLH_INTCEN       11   /* PCI INTC enable*/
#define INTCTRLH_INTDPRI      12   /* PCI INTD priority*/
#define INTCTRLH_INTDEN       15   /* PCI INTD enable*/
#define INTCTRLH_INTEPRI      16   /* PCI INTE priority*/
#define INTCTRLH_INTEEN       19   /* PCI INTE enable*/
#define INTCTRLH_RESERVEPRI   20
#define INTCTRLH_RESERVE      23
#define INTCTRLH_PCISPRI      24   /* PCI SERR priority*/
#define INTCTRLH_PCISEN       27   /* PCI SERR enable*/
#define INTCTRLH_PCIEPRI      28   /* PCI internal error priority*/
#define INTCTRLH_PCIEEN       31   /* PCI internal error enable*/


/*
** INTPPES register bits
*/

#define INTPPESL_INTAPOL      0
#define INTPPESL_INTAEDGE     1
#define INTPPESL_INTBPOL      2
#define INTPPESL_INTBEDGE     3
#define INTPPESL_INTCPOL      4
#define INTPPESL_INTCEDGE     5
#define INTPPESL_INTDPOL      6
#define INTPPESL_INTDEDGE     7
#define INTPPESL_INTEPOL      8
#define INTPPESL_INTEEDGE     9

#define ACTIVE_LOW            1
#define ACTIVE_HIGH           0

#define LEVEL_SENSITIVE       1
#define EDGE_SENSITIVE        0


#endif    /* End of _hal_h */