altoona.c

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C语言 代码 · 共 378 行

/*++
 
Copyright (c) 1998  Microsoft Corporation
 
Module Name:
 
    Altoona.c
 
Abstract:
 
    Initialization for Altoona platform
 
Author:
 
    John Cooper (johncoop) 98-Jun-18
 
Environment:
 
    Wince Rom Monitor
 
Revision History:
 
--*/

#include <windows.h>
#include <bootldr.h>
#include "alt_def.h"
#include "vrc5074.h"
#include "alt_io.h"
#include "pciinit.h"

VOID
AltoonaInitVrc5074(
    )
 
/*++
 
Routine Description:
 
    Initialize remaining registers not done in startup.s
 
Arguments:
 
    None.
 
Return Value:
 
    None.
 
--*/

{
    PVRC5074_CONTROL p5074 = (PVRC5074_CONTROL)(KSEG1_BASE + VRC5074_BASE);

    //
    // setup the PDARS
    // SDRAM PDAR already set up in startup.s
    //

    p5074->SDRAM1.Lo = 0;
    p5074->SDRAM1.Hi = 0;

    p5074->PCIW0.Lo = PCI_MEMORY_BASE | PDAR_32BITS | PDAR_128MB;
    p5074->PCIW0.Hi = 0;

    p5074->PCIW1.Lo = PCI_CONFIG_BASE | PDAR_32BITS | PDAR_64MB;
    p5074->PCIW1.Hi = 0;

    p5074->DCS2.Lo = FLASH_BASE1 | PDAR_MEMLOC | PDAR_32BITS | PDAR_16MB;//for 5476 board
    p5074->DCS2.Hi = 0;
    p5074->DCS3.Lo = FLASH_BASE | PDAR_MEMLOC | PDAR_32BITS | PDAR_16MB;//for 5476 board
    p5074->DCS3.Hi = 0;

// program the control register
	p5074->DCS4.Lo = 0x1400002f;
    p5074->DCS4.Hi = 0;
	p5074->LCST4.Lo= 0x000a820a;	

	//program DCS5 for DIP switch

    p5074->DCS5.Lo = 0x1300002f;
    p5074->DCS5.Hi = 0;
	p5074->LCST5.Lo= 0x000a820a;	

// modifications for 5476 board (sudhakar)
    
	p5074->LCST2.Lo = 0x000a863a;
	p5074->LCST3.Lo = 0x000a863a;
	p5074->LCNFG.Lo = 0x0fff0010;
	p5074->DCSFN.Lo = 0x00011111;
	p5074->DCSIO.Lo = 0x00000400; 
//end of modifications


  
#if 0
    p5074->DCSFN.Lo = 1;// open this for 5074
    p5074->DCSFN.Hi = 1;
#endif
    p5074->INTCS.Lo = VRC5074_BASE | PDAR_64BITS | PDAR_2MB;
    p5074->INTCS.Hi = 0;

    //
    // CPUSTAT register and disable interrupts
    //

    p5074->CPUSTAT.Lo = 0x0000001C;
    p5074->CPUSTAT.Hi = 0x00000000;
    p5074->INTCTRL.Lo = 0x00000000;
    p5074->INTCTRL.Hi = 0x00000000;

    //
    // Vrc5074 PCI Config space registers
    // (BARC, BAR0, BAR1 will be written by pci initialization code)
    //

    p5074->PCICMD = 0x06;
    p5074->CLSIZ = 0x04;
    p5074->BAR2.Lo = 0xFFFFFFFC;
    p5074->BAR2.Hi = 0x00000000;
    p5074->BAR3.Lo = 0xFFFFFFFC;
    p5074->BAR3.Hi = 0x00000000;
    p5074->BAR4.Lo = 0xFFFFFFFC;
    p5074->BAR4.Hi = 0x00000000;
    p5074->BAR5.Lo = 0xFFFFFFFC;
    p5074->BAR5.Hi = 0x00000000;
    p5074->BAR6.Lo = 0xFFFFFFFC;
    p5074->BAR6.Hi = 0x00000000;
    p5074->BAR7.Lo = 0xFFFFFFFC;
    p5074->BAR7.Hi = 0x00000000;
    p5074->BAR8.Lo = 0xFFFFFFFC;
    p5074->BAR8.Hi = 0x00000000;
    p5074->BARB.Lo = 0xFFFFFFFC;
    p5074->BARB.Hi = 0x00000000;

    //
    // Configure misc PCI control registers
    //

    p5074->PCIARB.Lo = 0x1100003F;
    p5074->PCIARB.Hi = 0x00500011;


    // The PCI enumerator will assign memory addresses above the non-zero
    // PCI_BUS0_MEM_BASE.  This allows the Vrc5476 BAR0 to map from PCI
    // memory address 0 (for PCI bus master access to system memory) while not
    // overlapping with the already limited device memory range.
    // Setting PCI_BUS0_MEM_BASE in PCIINIT0 adds the same offset to system
    // addresses that hit the PCIW0 range, thus allowing it to reach this
    // shifted range of addresses.
    // 
    p5074->PCIINIT0.Lo = PCI_BUS0_MEM_BASE | PCIINIT_TYPE_MEM | PCIINIT_ACCESS_32;
    p5074->PCIINIT0.Hi = 0;

    p5074->PCIINIT1.Lo = PCIINIT_TYPE_IO | PCIINIT_ACCESS_32;
    p5074->PCIINIT1.Hi = 0;

    p5074->PCICTRL.Lo = 0x80000000;
    p5074->PCICTRL.Hi = 0x20000000;

}

VOID
AltoonaInitM1543(
    )
 
/*++
 
Routine Description:
 
    Initialize M1543 SuperIO/Bridge chip
 
Arguments:
 
    None.
 
Return Value:
 
    None.
 
--*/

{

    PVUCHAR pConfigPort;
    ULONG Reg;

    //
    // Don't know why we do this, but NEC code does it with no comment
    //

    PCIConfig_Write(0,IDSEL_M1543,0,0x40,0xC01C);

    //
    // Define IDE,PMU,USB idsel line
    //

    PCIConfig_Write(0,IDSEL_M1543,0,0x58,0x7D);
    PCIConfig_Write(0,IDSEL_M1543,0,0x70,(0xA << 16));

    //
    // Programmable chips selects
    //

    PCIConfig_Write(0,IDSEL_M1543,0,0x54,((LED_BASE & 0xFF) << 8) |
                                          ((NVRAM_BASE & 0xFF) << 16) |
                                          (0x40 << 24) |
                                          (1 << (22 + 8)) |
                                          (1 << (21 + 8)));

    //
    // don't know why we need to read this back, but the plug/play
    // stuff below doesn't work
    // if we don't
    //

    PCIConfig_Read(0,IDSEL_M1543,0,0x40);

    //
    // Program the config port of Super i/o
    //

    pConfigPort = (PVUCHAR)(CONFIGPORT_BASE + KSEG1_BASE);

    //
    // enter configure mode
    //

    pConfigPort[0] = 0x51;
    FLUSH_WRITE_BUFFER;
    pConfigPort[0] = 0x23;
    FLUSH_WRITE_BUFFER;

    //
    // Configure registers
    //

#define CONFIG_PORT_WRITE(REG,VALUE) \
    pConfigPort[0] = REG; \
    FLUSH_WRITE_BUFFER; \
    pConfigPort[1] = VALUE; \
    FLUSH_WRITE_BUFFER; \
    pConfigPort[1]

    //
    // Select Parallel Port
    // Enable
    // Set base address
    // set irq7
    // set dma
    // set mode
    // set misc
    //

    CONFIG_PORT_WRITE(0x07,0x03);
    CONFIG_PORT_WRITE(0x30,0x01);
    CONFIG_PORT_WRITE(0x60,(PARALLEL_BASE & 0x00000300) >> 8);
    CONFIG_PORT_WRITE(0x61,(PARALLEL_BASE & 0x000000FF));
    CONFIG_PORT_WRITE(0x70,0x07);
    CONFIG_PORT_WRITE(0x74,0x04);
    CONFIG_PORT_WRITE(0xF0,0x00);
    CONFIG_PORT_WRITE(0xF4,0x80);

    //
    // Select Uart1
    // Enable
    // Set base address
    // choose irq3
    // clock select stuff
    //

    CONFIG_PORT_WRITE(0x07,0x04);
    CONFIG_PORT_WRITE(0x30,0x01);
    CONFIG_PORT_WRITE(0x60,(UART1_BASE & 0x00000300) >> 8);
    CONFIG_PORT_WRITE(0x61,(UART1_BASE & 0x000000FF));
    CONFIG_PORT_WRITE(0x70,0x04);
    CONFIG_PORT_WRITE(0xF0,0x00);
    CONFIG_PORT_WRITE(0xF1,0x00);
    CONFIG_PORT_WRITE(0xF2,0x00);

    //
    // Same for Uart2
    // except choose irq4
    //

    CONFIG_PORT_WRITE(0x07,0x05);
    CONFIG_PORT_WRITE(0x30,0x01);
    CONFIG_PORT_WRITE(0x60,(UART2_BASE & 0x00000300) >> 8);
    CONFIG_PORT_WRITE(0x61,(UART2_BASE & 0x000000FF));
    CONFIG_PORT_WRITE(0x70,0x03);
    CONFIG_PORT_WRITE(0xF0,0x00);
    CONFIG_PORT_WRITE(0xF1,0x00);
    CONFIG_PORT_WRITE(0xF2,0x00);

    //
    // Floppy disk controller
    // Enable
    // set base
    // Set IRQ5
    //

#if 0
    CONFIG_PORT_WRITE(0x07,0x00);
    CONFIG_PORT_WRITE(0x30,0x01);
    CONFIG_PORT_WRITE(0x60,(FLOPPY_BASE & 0x00000300) >> 8);
    CONFIG_PORT_WRITE(0x61,(FLOPPY_BASE & 0x000000FF));
    CONFIG_PORT_WRITE(0x70,0x05);
#endif
    
    //
    // Configure kbd/ms
    // Mouse - irq1
    // kbd - irq12
    //

    CONFIG_PORT_WRITE(0x07,0x07);
    CONFIG_PORT_WRITE(0x30,0x01);
    CONFIG_PORT_WRITE(0x70,0x01);
    CONFIG_PORT_WRITE(0x72,0x0C);
    CONFIG_PORT_WRITE(0xF0,0x00);

    //
    // return config port to RUN state
    //

    pConfigPort[0] = 0xBB;
    FLUSH_WRITE_BUFFER;

    //
    // Set IDE to irq14
    //

    Reg = PCIConfig_Read(0,IDSEL_M1543,0,0x44);
    Reg = (Reg & 0xFFFFFFF0) | 0xD;
    PCIConfig_Write(0,IDSEL_M1543,0,0x44,Reg);

    //
    // Set USB to IRQ5.
    // This interrupt stolen from Floppy disk controller
    //

    Reg = PCIConfig_Read(0, IDSEL_M1543, 0, 0x74);
    Reg = (Reg & 0xFFFFFF00) | 0x15;
    PCIConfig_Write(0, IDSEL_M1543, 0, 0x74, Reg);
}



VOID
AltoonaInit(
    )
 
/*++
 
Routine Description:
 
    Routine to initialize altoona hardware
 
Arguments:
 
    None.
 
Return Value:
 
    None.
 
--*/

{

    AltoonaInitVrc5074();
    AltoonaInitM1543();
    //ParalInit();

    WriteLED(0x00);      // display 0 to LED

}