igs2010.h
来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C头文件 代码 · 共 429 行 · 第 1/2 页
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#define reg_HWGC_BGSTK reg_CR[0x4B] // R/W Background color 3-entry stack
#define reg_HWGC_STA_H reg_CR[0x4C] // R/W Cursor storage start addr high
#define reg_HWGC_STA_L reg_CR[0x4D] // R/W Cursor storage start addr low
#define reg_HWGC_DX reg_CR[0x4E] // R/W Offset (for cursors off left of screen)
#define reg_HWGC_DY reg_CR[0x4F] // R/W Offset (for cursors off top of screen)
//
#define reg_EXT_SCTL_1 reg_CR[0x50] // R/W Pixel BPP & graphics engine stride
#define reg_EXT_SCTL_2 reg_CR[0x51] // R/W High bits of CR31, CR35, and CR13
#define reg_EXT_BBFLG1 reg_CR[0x52] // R/W BIOS flags
#define reg_EXT_MCTL_1 reg_CR[0x53] // R/W Enable write-perbit, enable MMIO access, swap nibbles
#define reg_EXT_MCTL_2 reg_CR[0x54] // R/W Number of mem access cyc avail
#define reg_EXT_DAC_CT reg_CR[0x55] // R/W X11/MS-win,VCLK tri-state
#define reg_EXT_SYNC_1 reg_CR[0x56] // R/W Genlock & tri-state control
#define reg_EXT_SYNC_2 reg_CR[0x57] // R/W For remote vsync
#define reg_LAW_CTL reg_CR[0x58] // R/W Linear address window control
#define reg_LAW_POS_H reg_CR[0x59] // R/W LAW address Bits 31:24
#define reg_LAW_POS_L reg_CR[0x5A] // R/W LAW address Bits 23:16
#define reg_GOUT_PORT reg_CR[0x5C] // R/W General out (to PCI)
#define reg_EXT_H_OVF reg_CR[0x5D] // R/W Bit 8(or+32/64) of CR 0,1,2,3,4,5,3B,5F
#define reg_EXT_V_OVF reg_CR[0x5E] // R/W Bit 10 of CR 6,12,15,10, 18
#define reg_EXT_MCTL_3 reg_CR[0x60] // R/W # 4 or 8 byte units / access grant
#define reg_EXT_SYNC_3 reg_CR[0x63] // R/W Sync adjust for genlock
#define reg_EXT_MISC_CTL reg_CR[0x65] // R/W Enable 3C3 (vs 46E8) for setup
#define reg_EXT_MISC_1 reg_CR[0x66] // R/W Interrupt PCI burst or tri-state pix add
#define reg_EXT_MISC_2 reg_CR[0x67] // R/W RAMDAC color mode (source Bpp), and DCLK phase
#define reg_CNFG_REG_3 reg_CR[0x68] // R/W RAS/CAS control - strapped
#define reg_EXT_SCTL_3 reg_CR[0x69] // R/W Bits [19:16] of display start address
#define reg_EXT_SCTL_4 reg_CR[0x6A] // R/W Bits [19:14] of CPU base address
#define reg_EBIOS_FLG3 reg_CR[0x6B] // R/W BIOS flags
#define reg_EBIOS_FLG4 reg_CR[0x6C] // R/W BIOS flags
#define reg_PIXEL_PIPE0 reg_XR[0x80] // R/W Pixel Pipeline Configuration 0
#define reg_CURSOR1_VERTEXT reg_XR[0xA1] // R/W Cursor 1 Veritcal Extension Register
#define reg_CURSOR1_XLOW reg_XR[0x50] // R/W Cursor 1 X position low
#define reg_CURSOR1_XHI reg_XR[0x51] // R/W Cursor 1 X position high
#define reg_CURSOR1_XPRESET reg_XR[0x52] // R/W Cursor 1 X horz. preset
#define reg_CURSOR1_YLOW reg_XR[0x53] // R/W Cursor 1 Y position low
#define reg_CURSOR1_YHI reg_XR[0x54] // R/W Cursor 1 Y position high
#define reg_CURSOR1_YPRESET reg_XR[0x55] // R/W Cursor 1 Y vert.. preset
#define reg_CURSOR1_CONTROL reg_XR[0x56] // R/W Cursor 1 Control Register, Sprite Control
#ifdef ENABLE_ACCELERATION
#define reg_MIN_AXIS_PCNT reg_BEE8[0x0] // Rectangle height for Blts etc
#define reg_SCISSORS_T reg_BEE8[0x1] // Top of clipping rect
#define reg_SCISSORS_L reg_BEE8[0x2] // Left of clipping rect
#define reg_SCISSORS_B reg_BEE8[0x3] // Bottom of clipping rect
#define reg_SCISSORS_R reg_BEE8[0x4] // Right of clipping rect
#define reg_PIXEL_CNTL reg_BEE8[0xA] // Select between mix registers
#define reg_MULT_MISC_2 reg_BEE8[0xD] // Selects which MB src & dest base starts in
#define reg_MULT_MISC reg_BEE8[0xE] // Select MB starts, Enables compares, Select 32-bit command regs
#define reg_READ_SEL reg_BEE8[0xF] // Select xxx for read of BEE8
#endif // ENABLE_ACCELERATION
#define reg_CUR_Y (MM_RW_16 m_pMMIO[0x82E8] ) // R/W Current Y position (12 bits)
#define reg_CUR_X (MM_RW_16 m_pMMIO[0x86E8] ) // R/W Current X position (12 bits)
#define reg_CUR_Y2 (MM_RW_16 m_pMMIO[0x82EA] ) // R/W Current Y position #2
#define reg_CUR_X2 (MM_RW_16 m_pMMIO[0x86EA] ) // R/W Current X position #2
#define reg_DESTY_AXSTP (MM_RW_16 m_pMMIO[0x8AE8] ) // R/W Dest Y for Blts, AXSTP for lines
#define reg_Y2_AXSTP2 (MM_RW_16 m_pMMIO[0x8AEA] ) // R/W Y2 for polygons & 4-point trapezoids, AXSTP2 for Bresn-trapezoids
#define reg_DESTX_DIASTP (MM_RW_16 m_pMMIO[0x8EE8] ) // R/W Dest X for Blts, DIASTP for lines
#define reg_X2 (MM_RW_16 m_pMMIO[0x8EEA] ) // R/W End X for 4-point traps, Diag step const for bresn-trapezoids
#define reg_ERR_TERM (MM_RW_16 m_pMMIO[0x92E8] ) // R/W Initial error term for lines
#define reg_ERR_TERM2 (MM_RW_16 m_pMMIO[0x92EA] ) // R/W Error term #2 for Bresn-trapezoids
#define reg_MAJ_AXIS_PCNT (MM_RW_16 m_pMMIO[0x96E8] ) // R/W Major axis pixel count
#define reg_MAJ_AXIS_PCNT2 (MM_RW_16 m_pMMIO[0x96EA] ) // R/W Major axis pixel count for 2nd line in Bresn-trapezoid
#define reg_GP_STAT (MM_RO_16 m_pMMIO[0x9AE8] ) // R FIFO Status & hardware busy
#define reg_CMD (MM_WO_16 m_pMMIO[0x9AE8] ) // W Drawing command, mode, ctrl
#define reg_CMD2 (MM_WO_16 m_pMMIO[0x9AEA] ) // W Direction of line2 for Bresn-trapezoids
#define reg_SHORT_STROKE (MM_WO_16 m_pMMIO[0x9EE8] ) // W Draws two short lines
#define reg_BKGD_COLOR (MM_RW_16 m_pMMIO[0xA2E8] ) // R/W Background color
#define reg_FRGD_COLOR (MM_RW_16 m_pMMIO[0xA6E8] ) // R/W Foreground color
#define reg_WRT_MASK (MM_RW_16 m_pMMIO[0xAAE8] ) // R/W Write mask
#define reg_RD_MASK (MM_RW_16 m_pMMIO[0xAEE8] ) // R/W Read mask
#define reg_COLOR_CMP (MM_RW_16 m_pMMIO[0xB2E8] ) // R/W Color compare value
#define reg_BKGD_MIX (MM_RW_16 m_pMMIO[0xB6E8] ) // R/W Background Mix (source & 4-bitROP)
#define reg_FRGD_MIX (MM_RW_16 m_pMMIO[0xBAE8] ) // R/W Foreground Mix (source & 4-bitROP)
#define reg_RD_REG_DT (MM_RO_16 m_pMMIO[0xBEE8] ) // R Read BEE8_xxx register
#define reg_PIX_TRANS (MM_WO_16 m_pMMIO[0xE2E8] ) // W Pixel data transfer (from CPU to eng)
#define reg_PIX_TRANS_EXT (MM_WO_16 m_pMMIO[0xE2EA] ) // W Bits 31:16 for PIX_TRANS
#define reg_PAT_Y (MM_RW_16 m_pMMIO[0xEAE8] ) // R/W Vert coord top edge of 8x8 pattern
#define reg_PAT_X (MM_RW_16 m_pMMIO[0xEAEA] ) // R/W Horiz coord left edge of 8x8 pattern
// 32-bit WRITE ONLY concatenated accelerator registers (0..15), (16..32)
#define reg_ALT_CURXY (MM_WO_32 m_pMMIO[0x8100] ) // CUR_Y, CUR_X
#define reg_ALT_CURXY2 (MM_WO_32 m_pMMIO[0x8104] ) // CUR_Y2, CUR_X2
#define reg_ALT_STEP (MM_WO_32 m_pMMIO[0x8108] ) // DESTY_AXSTP, DESTX_DIASTP
#define reg_ALT_STEP2 (MM_WO_32 m_pMMIO[0x810C] ) // Y2_AXSTP2, X2_DIASTP2
#define reg_ALT_ERR (MM_WO_32 m_pMMIO[0x8110] ) // ERR_TERM, ERR_TERM2
#define reg_ALT_CMD (MM_WO_32 m_pMMIO[0x8118] ) // CMD, CMD2
#define reg_ALT_MIX (MM_WO_32 m_pMMIO[0x8134] ) // BKGD_MIX, FRGD_MIX
#define reg_ALT_PCNT (MM_WO_32 m_pMMIO[0x8148] ) // MIN_AXIS_PCNT, MAJ_AXIS_PCNT
#define reg_ALT_PAT (MM_WO_32 m_pMMIO[0x8168] ) // PAT_Y, PAT_X
#define reg_XR_CRTVertCount0 reg_XR[0x18] // R/W CRT vertical counter 0
#define reg_XR_CRTVertCount1 reg_XR[0x19] // R/W CRT vertical counter 1
#define reg_XR_BIUMisc reg_XR[0x33] // R/W misc. BIU bits
#define reg_XR_ExtLinearAddress reg_XR[0x35] // R/W frame buffer high bits of address
#define reg_XR_FunctionControl reg_XR[0x3C] // R/W port enable, endian
#define reg_XR_X2VideoDisplayVertEnd reg_XR[0x4E] // R/W X2 video display vertical ending line high
#define reg_XR_SpriteControl reg_XR[0x56] // R/W sprite control & RAMDAC select
#define reg_XR_Ramdac reg_XR[0x5C] // R/W RAMDAC ?
#define reg_XR_MEMCTL2 reg_XR[0x72] // R/W memory controller 2
#define reg_CURSOR1_ADDRLOW reg_XR[0x7E] // R/W Cursor 1 base address low
#define reg_CURSOR1_ADDRHI reg_XR[0x7F] // R/W Cursor 1 base address high
#define reg_XR_ExtMiscClock reg_XR[0xB9] // R/W extended misc clock
#define reg_XR_ExtMClockNum0 reg_XR[0xB2] // R/W extended M Clock numerator 0
#define reg_XR_ExtMClockNum1 reg_XR[0xB3] // R/W extended M Clock numerator 1
#define reg_XR_ExtMiscClock reg_XR[0xB9] // R/W extended misc clock
#define reg_XR_IndirectIndexFor4x reg_XR[0xFA] // R/W indirect index for 4x
// memory mapped acceleration registers
#define reg_Page_Base (MM_RW_32 m_pMMIO[0x0000])
#define reg_Virtual_Addr (MM_RW_32 m_pMMIO[0x0004])
#define reg_Reserved08 (MM_RW_16 m_pMMIO[0x000E])
#define reg_State_A_Len (MM_RW_8 m_pMMIO[0x000C])
#define reg_State_B_Len (MM_RW_8 m_pMMIO[0x000D])
#define reg_Reserved0E (MM_RW_16 m_pMMIO[0x000E])
#define reg_Reserved10 (MM_RW_16 m_pMMIO[0x0010])
#define reg_Cop_control (MM_RW_8 m_pMMIO[0x0011])
#define reg_Px_Map_Index (MM_RW_8 m_pMMIO[0x0012])
#define reg_Reserved13 (MM_RW_16 m_pMMIO[0x0013])
#define reg_Px_Map_Base (MM_RW_32 m_pMMIO[0x0014])
#define reg_Src_Map_Width (MM_RW_16 m_pMMIO[0x0018])
#define reg_Src2_Map_Width (MM_RW_16 m_pMMIO[0x0118])
#define reg_Dst_Map_Width (MM_RW_16 m_pMMIO[0x0218])
#define reg_Px_Map_Height (MM_RW_16 m_pMMIO[0x001A])
#define reg_Px_Map_Format (MM_RW_8 m_pMMIO[0x001C])
#define reg_Reserved1D (MM_RW_16 m_pMMIO[0x001D])
#define reg_Reserved1E (MM_RW_16 m_pMMIO[0x001E])
#define reg_Reserved1F (MM_RW_16 m_pMMIO[0x001F])
#define reg_Bres_Err_Term (MM_RW_16 m_pMMIO[0x0020])
#define reg_Reserved22 (MM_RW_16 m_pMMIO[0x0022])
#define reg_Bres_K1 (MM_RW_16 m_pMMIO[0x0024])
#define reg_Reserved26 (MM_RW_16 m_pMMIO[0x0026])
#define reg_Bres_K2 (MM_RW_16 m_pMMIO[0x0028])
#define reg_Reserved2A (MM_RW_16 m_pMMIO[0x002A])
#define reg_Direction_Step (MM_RW_32 m_pMMIO[0x002C])
#define reg_Direction_StepL (MM_RW_16 m_pMMIO[0x002C])
#define reg_Direction_StepH (MM_RW_16 m_pMMIO[0x002C+0x2]);
#define reg_Reserved30 (MM_RW_16 m_pMMIO[0x0030])
#define reg_Reserved34 (MM_RW_16 m_pMMIO[0x0034])
#define reg_Reserved38 (MM_RW_16 m_pMMIO[0x0038])
#define reg_Reserved3C (MM_RW_16 m_pMMIO[0x003C])
#define reg_Reserved40 (MM_RW_16 m_pMMIO[0x0040])
#define reg_Reserved44 (MM_RW_16 m_pMMIO[0x0044])
#define reg_Fore_Mix (MM_RW_8 m_pMMIO[0x0048])
#define reg_Back_Mix (MM_RW_8 m_pMMIO[0x0049])
#define reg_Dest_Color_Comp (MM_RW_8 m_pMMIO[0x004A])
#define reg_Reserved4B (MM_RW_8 m_pMMIO[0x004B])
#define reg_Color_Comp_Val (MM_RW_32 m_pMMIO[0x004C);
#define reg_Px_Bit_Mask (MM_RW_32 m_pMMIO[0x0050])
#define reg_Carry_Chain_Mask (MM_RW_32 m_pMMIO[0x0054])
#define reg_Fore_Color (MM_RW_32 m_pMMIO[0x0058])
#define reg_Back_Color (MM_RW_32 m_pMMIO[0x005C])
#define reg_Op_Dimension_1 (MM_RW_16 m_pMMIO[0x0060])
#define reg_Op_Dimension_2 (MM_RW_16 m_pMMIO[0x0062])
#define reg_Reserved64 (MM_RW_16 m_pMMIO[0x0064])
#define reg_Reserved68 (MM_RW_16 m_pMMIO[0x0068])
#define reg_Mask_Map_X (MM_RW_16 m_pMMIO[0x006C])
#define reg_Mask_Map_Y (MM_RW_16 m_pMMIO[0x006E])
#define reg_Src_Base_Ptr (MM_RW_32 m_pMMIO[0x0070])
#define reg_Pattern_Map_X (MM_RW_16 m_pMMIO[0x0074])
#define reg_Pattern_Map_Y (MM_RW_16 m_pMMIO[0x0076])
#define reg_Dst_X_Phase (MM_RW_8 m_pMMIO[0x0078])
#define reg_Dst_Y_Phase (MM_RW_8 m_pMMIO[0x007A])
#define reg_Pat_Y_Phase (MM_RW_8 m_pMMIO[0x007A])
#define reg_Pat_X_Phase (MM_RW_8 m_pMMIO[0x0150])
#define reg_SLine_RoOv (MM_RW_8 m_pMMIO[0x0134])
#define reg_SLine_Incr (MM_RW_8 m_pMMIO[0x0135])
#define reg_SLine_Pttn (MM_RW_8 m_pMMIO[0x0136])
#define reg_SLine_Accu (MM_RW_8 m_pMMIO[0x0137])
#define reg_SLine_Indx (MM_RW_8 m_pMMIO[0x0138])
#define reg_Src_Start_Ptr (MM_RW_32 m_pMMIO[0x0170])
#define reg_Dst_Start_Ptr (MM_RW_32 m_pMMIO[0x0178])
#define reg_Px_Op (MM_RW_32 m_pMMIO[0x007C])
#define reg_Px_OpL (MM_RW_16 m_pMMIO[0x007C])
#define reg_Px_OpH (MM_RW_16 m_pMMIO[0x007C+0x2])
#define Mix_S 0x03
#define Right_Down 0x00000000
#define Left_Down 0x00000004
#define Right_Up 0x00000002
#define Left_Up 0x00000007 //for PxBlt direction
#define Fore_Src_color 0x00000000
#define Back_Src_color 0x00000000
#define Fore_Src_PxMap 0x20000000
#define Back_Src_PxMap 0x80000000
#define PxBlt 0x08000000
#define PxBlt_Invert 0x09000000
#define PxBlt_Area_Fill 0x0A000000
#define Pattern_PxMap_A 0x00001000
#define Pattern_PxMap_B 0x00002000
#define Pattern_PxMap_C 0x00003000
#define Pattern_Foreground 0x00008000
#define Pattern_From_Src 0x00009000
#endif __IGS2010_H__
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