config.cpp

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C++ 代码 · 共 653 行 · 第 1/2 页

/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 1995, 1996, 1997, 1998  Microsoft Corporation

Module Name:  

Abstract:  
  
Functions:


Notes: 
    ported from CT6555x driver  Dec.1997

--*/

#include "precomp.h"

// The dpCurSettings structure
INSTANTIATE_GPE_ZONES(0x3,"DDI Driver","unused1","unused2")  /* Start with Errors, warnings, and temporary messages */
//??INSTANTIATE_GPE_ZONES(0x2833,"DDI Driver","unused1","unused2")
//??INSTANTIATE_GPE_ZONES(0x1033,"DDI Driver","unused1","unused2")   
//??INSTANTIATE_GPE_ZONES(0x00F3,"DDI Driver","unused1","unused2")   //blts


#ifdef USE_MEMORY_MAPPED_PORTS
        // LinearBaseAddress is used globally from GPEVGA.CPP
        // because XR35 register does not seem to return the correct
        // value when using memoruy mapped registers
extern ULONG LinearBaseAddress; /*linear frame buffer pointer base address*/
#endif //USE_MEMORY_MAPPED_PORTS


// This gets around problems exporting from .lib
BOOL APIENTRY GPEEnableDriver(          
    ULONG          iEngineVersion,
    ULONG          cj,
    DRVENABLEDATA *pded,
    PENGCALLBACKS  pEngCallbacks);



//
//  DrvEnableDriver - main entry point
//  inputs:  
//  outputs: none
//
BOOL APIENTRY DrvEnableDriver(
    ULONG          iEngineVersion,
    ULONG          cj,
    DRVENABLEDATA *pded,
    PENGCALLBACKS  pEngCallbacks)
{
    //??DebugBreak();

    return GPEEnableDriver( iEngineVersion, cj, pded, pEngCallbacks );
}


#ifdef FB16BPP
extern ulong BitMasks[];    // 16 bpp
#else   // FP16BPP
#include "palette.h"    // for 8Bpp we use the natural palette
INSTANTIATE_PALETTE
#endif // FP16BPP

static GPE *pGPE = (GPE *)NULL;

//
//  GetGPE - Main entry point for a GPE-compliant driver
//  inputs:  none
//  outputs: none
//
GPE *GetGPE()
{
    if( !pGPE )
        pGPE = new IGS2010();
    return pGPE;
}


//
//  DumpVGARegs - dump the chips registers to the debugger
//  inputs:  none
//  outputs: none
//
void IGS2010::DumpVGARegs()
{
    ULONG   i;
#ifdef DEBUG
    BYTE bTemp;
#endif  // DEBUG
    
    DEBUGMSG (GPE_ZONE_HW, (TEXT("Dumping VGA Registers\r\n")));
    
    
    
    DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\nMSR   %02X;  FCR   %02X;\r\n"),
              bTemp = reg_MISC, bTemp = reg_FCR_WT));

    // SR Registers
    DEBUGMSG (GPE_ZONE_HW, (TEXT("Dumping SR\r\n")));
    for (i=0; i < REG_SR_SIZE; i++) {
        DEBUGMSG (GPE_ZONE_HW, (TEXT("SR%02X  %02X;  "), i, bTemp = reg_SR[i]));
        if (i % 2) {
            DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\n")));
        }
    }
    DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\n")));

    // CR registers
    DEBUGMSG (GPE_ZONE_HW, ((TEXT("Dumping CR\r\n"))));
    for (i=0; i < REG_CR_SIZE; i++) {
        DEBUGMSG (GPE_ZONE_HW, (TEXT("CR%02X  %02X;  "), i, bTemp = reg_CR[i]));
        if (i % 2) {
            DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\n")));
        }
    }
    DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\n")));

    // GR registers
    DEBUGMSG (GPE_ZONE_HW, (TEXT("Dumping GR\r\n")));
    for (i=0; i < REG_GR_SIZE; i++) {
        DEBUGMSG (GPE_ZONE_HW, (TEXT("GR%02X  %02X;  "), i, bTemp = reg_GR[i]));
        if (i % 2) {
            DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\n")));
        }
    }
    DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\n")));

    // AR registers
    DEBUGMSG (GPE_ZONE_HW, (TEXT("Dumping AR\r\n")));
    for (i=0; i < REG_AR_SIZE; i++) {
        reg_AR.ResetToAddr();
        DEBUGMSG (GPE_ZONE_HW, (TEXT("AR%02X  %02X;  "), i, bTemp = reg_AR[i]));
        if (i % 2) {
            DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\n")));
        }
    }
    DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\n")));

    // XR registers
    DEBUGMSG (GPE_ZONE_HW, (TEXT("Dumping XR\r\n")));
    //??for (i=0; i < REG_XR_SIZE; i++) {
    for (i=0; i < 0xFF; i++) {
        DEBUGMSG (GPE_ZONE_HW, (TEXT("XR%02X  %02X;  "), i, bTemp = reg_XR[i]));
        if (i % 2) {
            DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\n")));
        }
    }
    DEBUGMSG (GPE_ZONE_HW, (TEXT("\r\n")));

    Sleep (DBG_SLEEP);
    DEBUGMSG (GPE_ZONE_HW, (TEXT("Leaving DumpVGARegs()\r\n")));
}


//
//  IGS201 Constructor
//  inputs:  none
//  outputs: none
//
IGS2010::IGS2010()
{
    BYTE    bTemp;
    ULONG inIoSpace = 0;
    PHYSICAL_ADDRESS ioPhysicalBase = { LinearBaseAddress, 0 };
                
    DEBUGMSG( GPE_ZONE_INIT,(TEXT("IGS2010::IGS2010\r\n")));

#ifdef MIPS
	//	[stjong] 10/02/98
	//	a HACK for normal IGS card to run in memory mode.
	//	Microsoft's IGS card has the pull up resistor that sets the default mode to Memory Mapped mode.
	//	On the sample IGS card from IGST, the pull up is not implemented and hence the video card default to IO mode.
	//	This driver (by Paul) assumes Memory Mapped mode.
	//	The fix below is from IGST, it basically goes into the standard IO port (for vga) and turn the chip to 
	//	IO mode hence eliminating the need for pull up.
	
	BOOL	bKMode;
	PBYTE	pIO_46E8	= (PBYTE) 0xb80046e8;
	PBYTE	pIO_102		= (PBYTE) 0xb8000102;
	PBYTE	pIO_3CE		= (PBYTE) 0xb80003ce;
	PBYTE	pIO_3CF		= (PBYTE) 0xb80003cf;	

	bKMode = SetKMode (TRUE);

	*pIO_46E8 = 0x18;
	*pIO_102  = 0x01;	
	*pIO_46E8 = 0x08;

	
	*pIO_3CE  = 0x33;
	*pIO_3CF  = 0x01;

	SetKMode (bKMode);
#endif


#ifdef USE_MEMORY_MAPPED_PORTS
        // LinearBaseAddress is used globally
        // because XR35 register does not seem to return the correct
        // value when using memory mapped registers
    m_nLAWPhysical = LinearBaseAddress;
#else  //USE_MEMORY_MAPPED_PORTS
        // get the linear frame buffer address from the extension mapped 
        // PCI base address register
    UCHAR lowAddress = 0;
    UCHAR highAddress = reg_XR_ExtLinearAddress;
    m_nLAWPhysical = (((ULONG)highAddress) << 24) | (((ULONG)lowAddress) << 20);
    LinearBaseAddress = m_nLAWPhysical;
#endif  //USE_MEMORY_MAPPED_PORTS

    DEBUGMSG( GPE_ZONE_INIT,(TEXT("LAWPhysical is at: 0x%08x\r\n"), m_nLAWPhysical ));

        // get the video memory size
    m_nVideoMemorySize = reg_XR_MEMCTL2 & 0x3;
    switch(m_nVideoMemorySize) {
        case 0:
            m_nVideoMemorySize = 1024 * 1024;     // 1MB
            DEBUGMSG( GPE_ZONE_INIT,(TEXT("IGS2010: 1MB FrameBuffer\r\n")));
            break;
        case 1:
            m_nVideoMemorySize= 2 * 1024 * 1024;  // 2MB
            DEBUGMSG( GPE_ZONE_INIT,(TEXT("IGS2010: 2MB FrameBuffer\r\n")));
            break;
        case 2:
            m_nVideoMemorySize= 4 * 1024 * 1024; // 4MB
            DEBUGMSG( GPE_ZONE_INIT,(TEXT("IGS2010: 4MB FrameBuffer\r\n")));
            break;
        default:
            m_nVideoMemorySize= 4 * 1024 * 1024; // ?MB
            DEBUGMSG( GPE_ZONE_INIT,(TEXT("IGS2010: FrameBuffer size unknown\r\n")));
            break;
    }


    m_pLAW = (unsigned char *)VirtualAlloc(0, m_nVideoMemorySize, MEM_RESERVE, PAGE_NOACCESS );

    DEBUGMSG( GPE_ZONE_INIT,(TEXT("VirtualAlloc of LAW returns 0x%08x\r\n"), m_pLAW));

    if (HalTranslateBusAddress(PCIBus, 0, ioPhysicalBase, &inIoSpace, &ioPhysicalBase)) {

        m_nLAWPhysical = ioPhysicalBase.LowPart; 

        // map the physical pages into the virtual region
        VirtualCopy(m_pLAW, (LPVOID)(m_nLAWPhysical>>8), m_nVideoMemorySize,
                    PAGE_READWRITE|PAGE_NOCACHE|PAGE_PHYSICAL);

    }
    else {
        DEBUGMSG (GPE_ZONE_ERROR, (TEXT("IGS2010: Can not translate bus address\r\n")));
    }

#ifdef TVOUT
        // map the TV memory mnapped registers in
    m_pTvRegs = (unsigned char *)VirtualAlloc(0, TV_REG_SIZE, MEM_RESERVE, PAGE_NOACCESS );

    DEBUGMSG( GPE_ZONE_INIT,(TEXT("VirtualAlloc of m_pTvRegs returns 0x%08X, mapping: 0x%X\r\n"),
                m_pTvRegs, ((m_nLAWPhysical | TV_MEMORY_OFFSET) >>8)));

        // map the physical pages into the virtual region
    VirtualCopy(m_pTvRegs, (LPVOID)((m_nLAWPhysical | TV_MEMORY_OFFSET) >>8), TV_REG_SIZE,
                PAGE_READWRITE|PAGE_NOCACHE|PAGE_PHYSICAL);
#endif //TVOUT

        // enable the chip
    reg_SETUP_MD = 0x18;
    reg_POS = 0x01; // Global Enable register ( = 0x102)
    reg_SETUP_MD = 0x08;
        // following code is currently required, to be removed later, per IGS
        /*choose voltage reference*/
    reg_XR_SpriteControl = 0x04;    // RAMDAC address select
    reg_RAMDACMASK = 0x04;          // use VREF
    *reg_XR.m_pDataPort = 0x00;
    reg_XR_SpriteControl = 0x00;


    reg_MISC = 0xEF;   // Use color address range  ( = 0x3C2 write, 0x3CC read )
    
    unsigned char checkChip = reg_MISC;     // read from 0x3CC
    DEBUGMSG( GPE_ZONE_INIT,(TEXT("reg_MISC reads back as %02X\r\n"), checkChip ));


#ifdef ENABLE_ACCELERATION
    // Map in memory mapped range of registers
    DEBUGMSG( GPE_ZONE_INIT,(TEXT("VirtualAlloc accelerator registers\r\n")));

    m_pMMIO = (PBYTE)VirtualAlloc(0, ACCEL_REG_SIZE, MEM_RESERVE, PAGE_NOACCESS);

    DEBUGMSG( GPE_ZONE_INIT,(TEXT("VirtualAlloc of MMIO returns 0x%08X, mapping: 0x%X\r\n"),
                m_pMMIO, ((m_nLAWPhysical | ACCEL_MEMORY_OFFSET) >>8)));

        // map the physical pages into the virtual region
    VirtualCopy(m_pMMIO, (LPVOID)((m_nLAWPhysical | ACCEL_MEMORY_OFFSET) >>8), ACCEL_REG_SIZE,
                PAGE_READWRITE|PAGE_NOCACHE|PAGE_PHYSICAL);

#endif  // ENABLE_ACCELERATION

#ifdef FB16BPP
    SetMode640x480x16();
#else   // FB16BPP
    SetMode640x480x8();
#endif   // FB16BPP
#ifdef ENABLE_ACCELERATION
    // Initialize access to indexed ranges of registers
   DEBUGMSG( GPE_ZONE_INIT,(TEXT("Initialize access to m_pMMIO[]\r\n")));
   reg_XR_BIUMisc = 0x0F;
    // set the source distination accelerator width
    reg_Src_Map_Width  = 639;
    reg_Dst_Map_Width  = 639;
#ifdef FB16BPP
    reg_Px_Map_Format  = 1;
#else  //FB16BPP
    reg_Px_Map_Format  = 0;
#endif  //FB16BPP
#endif  // ENABLE_ACCELERATION

    DumpVGARegs();

    // Try reading/writting to FrameBuffer
    *m_pLAW = 0x55;
    bTemp = *m_pLAW;
    if (bTemp != 0x55) {