gpevga.cpp

来自「WinCE 3.0 BSP, 包含Inter SA1110, Intel_815」· C++ 代码 · 共 642 行 · 第 1/2 页

    PCI_COMMON_CONFIG   pciConfig;
    int                 bus, device, function;
    int                 length;

    for (bus = 0; bus < PCI_MAX_BUS; bus++) {
        for (device = 0; device < PCI_MAX_DEVICES; device++) {
            slotNumber.u.bits.DeviceNumber = device;

            for (function = 0; function < PCI_MAX_FUNCTION; function++) {
                slotNumber.u.bits.FunctionNumber = function;

                length = HalGetBusData(
                    PCIConfiguration, bus, slotNumber.u.AsULONG,
                    &pciConfig, 
                    sizeof(pciConfig) - sizeof(pciConfig.DeviceSpecific));

                if ((length == 0) || (pciConfig.VendorID == 0xFFFF)) {
                    break;
                }

                if ((wVendorId == pciConfig.VendorID) && 
                    (wDeviceId == pciConfig.DeviceID)) {
                    *pdwBusNumber = bus;
                    *ppPciSlotNumber = slotNumber;
                    *pPciCommonConfig = pciConfig;
                    return TRUE;
                }
            }
        }
    }
    return FALSE;
}
#endif //USE_MEMORY_MAPPED_PORTS


#ifdef TVOUT
//  TV Programming
//
//  PciFindDevice - 
//  inputs:  
//  outputs: none
//
VOID GPEVGA::SetTvMode()
{
     /*save ext_reg_33 and ext_reg_3C*/
    m_Reg33 = reg_XR_BIUMisc;
    m_Reg3C = reg_XR_FunctionControl;

    EnableTV(TRUE);

    SetTVReg(TV640x480x60, sizeof(TV640x480x60)/4);

    TVOn(TRUE);

    SetTVColor();
#ifdef FB16BPP
    BypassMode(TRUE);
#else //FB16BPP
    BypassMode(FALSE);
        //?? need to reset RAMDAC?
#endif  //FB16BPP
#ifdef INTERPOLATION
        // set TV out interpolation
    SetInterpolation();
#endif //INTERPOLATION
}
//
//  SetTVReg - Program TV registers.
//  inputs:  wPtr - a WORD pointer to an array of TV register settings
//           iCounter - counter of the TV registers.
//  outputs: none
//
VOID GPEVGA::SetTVReg(const WORD *wPtr, int iCounter)
{
    WORD wTVIndex, wTVValue;

    for (USHORT ii=0; ii < iCounter; ii++) {
      wTVIndex = *wPtr++;
      wTVValue = *wPtr++;

      WriteTVReg(wTVIndex, wTVValue);
    }
}

//
//  ReadTVReg - Read a 16-bit value from a TV register
//  inputs:  Index - TV register index.
//  outputs: Return a 16-bit value of the TV register
//
USHORT GPEVGA::ReadTVReg(WORD index)
{
    WORD value;

    BYTE valueL;
    BYTE valueH;

    UnlockTVReg();
    valueL =  *(PUCHAR)((m_pTvRegs) + index);
    valueH =  *(PUCHAR)((m_pTvRegs) + index + 1);

    value = (USHORT) (valueL + (valueH << 8) );

    LockTVReg();

    return value;
}

//
//  WriteTVReg - Write a 16-bit value into a TV register
//  inputs:  Index - TV register index.
//           data  - data to write
//  outputs: none
//
VOID GPEVGA::WriteTVReg(WORD index, WORD data)
{
    UnlockTVReg();
                                 
    *((USHORT *)(m_pTvRegs + index)) = data;

    LockTVReg();
}

//
//  UnlockTVReg - Allow the access to TV registers
//  inputs:  none
//  outputs: none
//
VOID GPEVGA::UnlockTVReg(VOID)
{
    reg_XR_BIUMisc = (m_Reg33 | 0x08);
    reg_XR_FunctionControl = (m_Reg3C | 0x80);
}

//
//  LockTVReg - Deny the access to TV registers
//  inputs:  none
//  outputs: none
//
VOID GPEVGA::LockTVReg(VOID)
{
    reg_XR_FunctionControl = m_Reg3C;
    reg_XR_BIUMisc = m_Reg33;
}


//
//  EnableTV - Enable or Disable TV out
//  inputs:  none
//  outputs: none
//
VOID GPEVGA::EnableTV(BOOLEAN iOnOff)
{
    BYTE iTmp;

    reg_XR_IndirectIndexFor4x = 0x05;   /*Banking I/O control*/

    if (iOnOff) {
      iTmp = reg_XR_X2VideoDisplayVertEnd & ~0x05;  /*bit <2,0>*/ 
      //if (iTVType == cpNTSC)
        reg_XR_X2VideoDisplayVertEnd = iTmp | 0x04;
      //else if (iTVType == PAL)
        //outportb(EXTDATA, iTmp | 0x05);
    } else {
      iTmp = reg_XR_X2VideoDisplayVertEnd & ~0x04;
      reg_XR_X2VideoDisplayVertEnd = iTmp;
    }
}


//
//  TVOn - Turn on or turn off TV.
//  inputs:  iOnOff - TRUE on
//  outputs: none
//
VOID GPEVGA::TVOn(BOOLEAN iOnOff)
{
    UCHAR iTmp;

    if (iOnOff) {
        iTmp = reg_XR_Ramdac;
        reg_XR_Ramdac = iTmp | 0x20;
    } else {
        iTmp = reg_XR_Ramdac;
        reg_XR_Ramdac = iTmp & ~0x20;
    }
}

//
//  SetTVColor - It corrects TV color each time when a new mode is set
//  inputs:  none
//  outputs: none
//
VOID GPEVGA::SetTVColor()
{
     BYTE bData;
     int  iTmp;
     WORD wTmp1;

     DEBUGMSG( GPE_ZONE_INIT, ( TEXT("Setting Tv Color\r\n")));
     wTmp1 = ReadTVReg(0xE4FC);      /*save regs*/

     WriteTVReg(0xE4FC, 0xC0C0);

     BypassMode(FALSE);           /*disable bypass mode*/

    // set RAMDAC to blue
    reg_DAC_WR_AD =0;
    for(USHORT ii=0; ii < 256; ii++ ) {
        reg_DAC_DATA = 0x00;
        reg_DAC_DATA = 0x00;
        reg_DAC_DATA = 0xFF;
    }

    /* Reset FSC: 3CE_4E<1>=1 */
    reg_XR_IndirectIndexFor4x = 0x05;
    reg_XR_X2VideoDisplayVertEnd = reg_XR_X2VideoDisplayVertEnd | 0x02;

    bData = 0;
    /* Wait for Vertical Display Enable */
    while ( ( reg_STATUS_1 & 0x08 ) == 0x00) { /*search until 1*/
        ;
    }
    while ( ( reg_STATUS_1 & 0x08 ) != 0x00) {  /*search until 0	active low*/
        ;
    }
    do { /*Wait for display scan line gets into middle of the screen*/
       iTmp  =    (WORD)(reg_XR_CRTVertCount0);
       iTmp +=  ( (WORD)(reg_XR_CRTVertCount1 & 0x07) << 8);
     } while ( (iTmp < 440/2) || (iTmp > 440) );
     //??need to add y-dimension var
     //while ( (iTmp < y_ext/2) || (iTmp > y_ext) );

     if (reg_XR_Ramdac & 0x80) {
         bData++;
     }
     iTmp = (WORD) bData;
     if (bData) {
       bData = 0x00;
     } else {
       bData = 0x08;     /*for toggle color bit<3>*/
     }

    /* clear FSC: 3CE_4E<1>=0 and toggle 3CE_4E<3> accordingly */
     reg_XR_IndirectIndexFor4x = 0x05;
     reg_XR_X2VideoDisplayVertEnd = (reg_XR_X2VideoDisplayVertEnd & ~0x02) ^ bData;
     WriteTVReg(0xE4FC,wTmp1);   /*restore regs*/
}

//
//  BypassMode - 
//  inputs:  iOnOff - True on
//  outputs: none
//
VOID GPEVGA::BypassMode(BOOLEAN iOnOff)
{
    BYTE bTmp;

    bTmp = reg_XR_SpriteControl;
    reg_XR_SpriteControl = bTmp | 0x04;
    if (iOnOff) {
        reg_RAMDACMASK = reg_RAMDACMASK  | 0x10;
    } else {
    reg_RAMDACMASK = reg_RAMDACMASK  & ~0x10;
    }
    reg_XR_SpriteControl = bTmp & ~0x04;
}

//
//  BypassMode - Enableinterpolation in underscan mode
//  inputs:  none
//  outputs: none
//
VOID GPEVGA::SetInterpolation()
{
    BYTE bTmp;

    for (ULONG ii = 0; ii < sizeof(I640x480x60_3CE)/2; ii+=2) {
            // set index and data
        reg_XR[I640x480x60_3CE[ii]] = I640x480x60_3CE[ii+1];
    }
    reg_XR_SpriteControl = reg_XR_SpriteControl  | 0x40;

//    if (iBpp == 8)
#ifndef FB16BPP
    for (ULONG ii = 0; ii < sizeof(I640x480x8x60_3D4)/2; ii+=2) {
         reg_CR[I640x480x8x60_3D4[ii]] = I640x480x8x60_3D4[ii+1];
    }
#else  //FB16BPP   else
    for (ii = 0; ii < sizeof(I640x480x16x60_3D4)/2; ii+=2) {
         reg_CR[I640x480x16x60_3D4[ii]] = I640x480x16x60_3D4[ii+1];
    }
#endif  //FB16BPP

    if (GetBusWidth() == 0) { /* only need to change if it is 32 bit bus */
        /* fetch register low*/
        bTmp = reg_EXT_MODE;

        if (bTmp & 0x80) {    /*overflow bit*/
            //outportb(CRTINDEX, 0x42);  /*overflow bits of fetch register: <5,4>*/
            //outportb(CRTDATA, inportb(CRTDATA) | 0x10);
            reg_MODE_CTL = reg_MODE_CTL  | 0x10;
        }

        bTmp = bTmp << 1;
        reg_EXT_MODE = bTmp;
    }
}

//
//  BypassMode - obtain current video memory bus width
//  inputs:  none
//  outputs: Return 0: 32 bits; 1: 64 bits
//
USHORT GPEVGA::GetBusWidth(VOID)
{
    BYTE bData;
    bData = reg_XR_MEMCTL2 & 0x04;  /*0: 32 bits; 1: 64 bits.*/
    return (bData >> 2);
}
#endif