cache.s

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

;++
; Copyright (c) 1997  Microsoft Corporation
;
; Module Name:
;    cache.s
;
; Abstract:
;    This module implements the code necessary to manage the CPU caches on the
; ARM processor.
;--
	OPT	2	; disable listing
	INCLUDE kxarm.h
	OPT	1	; reenable listing
	OPT	128	; disable listing of macro expansions




  IF _TGTCPU = "SA1100"
    INCLUDE cach1100.s
  ENDIF

  IF _TGTCPU = "ARM720"
    INCLUDE cache720.s
  ENDIF

  IF _TGTCPU = "ARM920"
    INCLUDE cache920.s
  ENDIF


	TEXTAREA

	LEAF_ENTRY OEMARMCacheMode
;++
; Routine Description:
;    Sets the C and B bits to be used to build page tables
;
; C and B bits are part of the page table entries and control write through vs. write back cache
; modes, cacheability, and write buffer use. Note that C and B bit functionality is processor 
; specific and different for the 720, 920, and SA1100. Consult the CPU hardware manual for the CPU 
; in question before altering these bit configurations!!
; This default configuration (C=B=1)works on all current ARM CPU's and gives the following behaviour
; ARM720: write through, write buffer enabled
; ARM920: write back cache mode
; SA1100: write back, write buffer enabled
;
; The four valid options are:
;	ARM_NoBits		0x00000000
; 	ARM_CBit		0x00000008
; 	ARM_BBit		0x00000004
; 	ARM_CBBits		0x0000000C
;
; Syntax:
;	DWORD OEMARMCacheMode(void);
;
; Arguments:
;	-- none --
;
; Return Value:
;	r0 must contain the desired C and B bit configuration. See description above for valid bit patterns.
;
; Caution: 
;	The value placed in r0 MUST be an immediate data value and NOT a predefined constant. This function
; 	is called at a point in the boot cycle where the memory containing predefined constants has NOT been 
;	initialized yet. 
;--
	mov	r0, #0x0000000C

  IF Thumbing
    bx  lr
  ELSE
    mov pc, lr          ; return
  ENDIF

    END