p2.h

WinCE 3.0 BSP, 包含Inter SA1110, Intel_815E, Advantech_PCM9574 等

#define TOUCH_SAMPLE_VALID		 0x03ff		// Bits which are valid in a touch panel sample
#define TOUCH_MAX_COORD			 12			// Max coord count = max coords * 2 = 6 * 2 = 12
#endif //TOUCH_AUDIO_UCB1100

#ifdef  TOUCH_AUDIO_CRYSTAL
#define TOUCH_SAMPLE_VALID		 0x0fff		// Bits which are valid in a touch panel sample
#define TOUCH_MAX_COORD		 	16			// Max coord count = max coords * 2 = 8 * 2 = 16
#endif //TOUCH_AUDIO_CRYSTAL

#define TOUCH_CHG_BUF_MASK		 0x10		// Mask XOR'd with a buf address to get other buf address
#define TOUCH_X_REQ			 0x4400		// Request an X coordinate
									// This enables doSample, sets adcSel to 00 = get an X coord
									// and leaves the timer enabled
#define TOUCH_Y_REQ			 0x4c00		// Request a Y coordinate
									// This enables doSample, sets adcSel to 01 = get a Y coord
									// and leaves the timer enabled

#endif // defined(MIPS) || defined(PPC)

/*
 * PCMCIA defines
 */

/*
 * PCMCIA Control register
 */
#define PCMCIA_ENABLE			0x40
#define PCMCIA_RESET			0x20
#define PCMCIA_INTR_MASK		0x10
#define PCMCIA_STATE_INTR_MASK	0x08
#define PCMCIA_MEM_WINDOW		0x07

/*
 * PCMCIA Interrupt register
 */
#define PCMCIA_WP			0x10
#define PCMCIA_CD2			0x08
#define PCMCIA_CD1			0x04
#define PCMCIA_INTR			0x02
#define PCMCIA_STATE_INTR		0x01

/*
 * PCMCIA Status register
 */
#define PCMCIA0_BVD1			0x8000
#define PCMCIA0_BVD2			0x4000
#define PCMCIA1_BVD1			0x2000
#define PCMCIA1_BVD2			0x1000
#define PCMCIA0_VSW1			0x0800
#define PCMCIA1_VSW1			0x0400
#define PCMCIA0_VSW2			0x0200
#define PCMCIA1_VSW2			0x0100

/*
 * PCMCIA Register addresses
 */
#define PCMCIA_REG0			    0x10	
#define PCMCIA_INTR_REG0		0x14	
#define PCMCIA_REG1			    0x18	
#define PCMCIA_INTR_REG1		0x1C	

#define PCMCIA_STATUS_REG		0x00	// Offset from PCMCIA_STATUS_BASE		
#define PCMCIA_CTL_REG			0x00    // Offset from PCMCIA_STATUS_BASE	


/*
 * CPU specific PCMCIA defines
 */

//
// SH3 PCMCIA config
//
#ifdef SH3
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		0x1B000000  // real physical address

#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x800000	// Only 8 Mbyte mapped in system address space
#define PCMCIA_NUM_WINDOWS     		10	

#define PCMCIA0_8_ATTR_WIN_BASE 	0x18000000
#define PCMCIA1_8_ATTR_WIN_BASE 	0x18800000
#define PCMCIA0_16_ATTR_WIN_BASE 	0x14000000
#define PCMCIA1_16_ATTR_WIN_BASE 	0x14800000
#define PCMCIA_ATTR_WIN_SIZE    	0x00200000		// 2 MB

#define PCMCIA0_8_CMN_WIN_BASE  	0x19000000
#define PCMCIA1_8_CMN_WIN_BASE  	0x19800000
#define PCMCIA0_16_CMN_WIN_BASE  	0x15000000
#define PCMCIA1_16_CMN_WIN_BASE  	0x15800000
#define PCMCIA_CMN_WIN_SIZE     	0x00800000    	// 8 MB

#define PCMCIA0_8_IO_WIN_BASE     	0x1A000000
#define PCMCIA1_8_IO_WIN_BASE     	0x1A800000

#define PCMCIA_IO_WIN_SIZE      	0x00200000     	// 2 MB

#endif  // SH3


//
// SH4 PCMCIA config
//
#ifdef SH4
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		0x1B000000  // real physical address

//
// The SH4 PCMCIA controller is integrated with the CPU paging mechanism, so
// really on an SH4 there is an almost unlimited number of PCMCIA windows that
// support all the variations (I/O, attribute, common, 8 bit, 16 bit).
//
#define PCMCIA_NUM_WINDOWS     		6
#define PCMCIA_WIN_SIZE     	0x03000000

#define PCMCIA0_WIN_BASE 	0x14000000
#define PCMCIA0_CMN_BASE    PCMCIA0_WIN_BASE
#define PCMCIA0_ATTR_BASE   PCMCIA0_WIN_BASE
#define PCMCIA0_IO_BASE     PCMCIA0_WIN_BASE

#define PCMCIA1_WIN_BASE 	0x18000000
#define PCMCIA1_CMN_BASE    PCMCIA1_WIN_BASE
#define PCMCIA1_ATTR_BASE   PCMCIA1_WIN_BASE
#define PCMCIA1_IO_BASE     PCMCIA1_WIN_BASE
#endif  // SH4

//
// R3910 PCMCIA config
//
#ifdef R3910
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		(SYSTEM_ASIC_REGS_BASE + 0x400)
#undef PCMCIA_STATUS_REG
#undef PCMCIA_CTL_REG
#define PCMCIA_STATUS_REG		0x20	// Offset from PCMCIA_STATUS_BASE		
#define PCMCIA_CTL_REG			0x20    // Offset from PCMCIA_STATUS_BASE	

#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x2000000	// 32 Mbytes mapped in system address space
#define PCMCIA_NUM_WINDOWS     		10	

#define PCMCIA0_8_ATTR_WIN_BASE 	0x0d000000
#define PCMCIA1_8_ATTR_WIN_BASE 	0x0f000000
#define PCMCIA0_16_ATTR_WIN_BASE 	0x0d000000
#define PCMCIA1_16_ATTR_WIN_BASE 	0x0f000000
#define PCMCIA_ATTR_WIN_SIZE    	0x01000000		// 16 MB

#define PCMCIA0_8_CMN_WIN_BASE  	0x68000000
#define PCMCIA1_8_CMN_WIN_BASE  	0x6a000000
#define PCMCIA0_16_CMN_WIN_BASE  	0x68000000
#define PCMCIA1_16_CMN_WIN_BASE  	0x6a000000
#define PCMCIA_CMN_WIN_SIZE     	0x02000000  	// actually is 64 Mbyte

#define PCMCIA0_8_IO_WIN_BASE     	0x0c000000
#define PCMCIA1_8_IO_WIN_BASE     	0x0e000000

#define PCMCIA_IO_WIN_SIZE      	0x01000000  	// 16 MB
#endif // R3910

//
// R3912 PCMCIA config
//
#ifdef R3912
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		0x0F000000  // real physical address

// We can not use 8bit and 16bit port simultaneously by R3912 restriction.
#define PCMCIA_NUM_WINDOWS     		6

#define PCMCIA0_ATTR_WIN_BASE 	0x66000000
#define PCMCIA1_ATTR_WIN_BASE 	0x6A000000
#define PCMCIA_ATTR_WIN_SIZE   	0x02000000		    // 32 MB

#define PCMCIA0_CMN_WIN_BASE  	0x64000000
#define PCMCIA1_CMN_WIN_BASE  	0x68000000
#define PCMCIA_CMN_WIN_SIZE    	0x02000000  		// 32 MB

#define PCMCIA0_IO_WIN_BASE    	0x08000000
#define PCMCIA1_IO_WIN_BASE    	0x0c000000
#define PCMCIA_IO_WIN_SIZE      0x02000000  		// 32 MB
#endif // R3912

//
// R4101 PCMCIA config  (PCMCIA currently not supported on R4101)
//
#ifdef R4101
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		0xb5180000

// The 4101 window is so small that there is a sep base address window
#define PCMCIA_ADDR_REG0		0x12	
#define PCMCIA_ADDR_REG1		0x1a	

#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x00020000	// Only 128 Kbyte mapped in system address space
#define PCMCIA_NUM_WINDOWS     		10

#define PCMCIA0_8_ATTR_WIN_BASE 	(PHYSICAL_ADDR_OFFSET + 0x15140000)
#define PCMCIA1_8_ATTR_WIN_BASE 	(PHYSICAL_ADDR_OFFSET + 0x151c0000)
#define PCMCIA0_16_ATTR_WIN_BASE 	(PHYSICAL_ADDR_OFFSET + 0x15140000)
#define PCMCIA1_16_ATTR_WIN_BASE 	(PHYSICAL_ADDR_OFFSET + 0x151c0000)

#define PCMCIA_ATTR_WIN_SIZE    	0x00020000		// 128 K

#define PCMCIA0_8_CMN_WIN_BASE  	(PHYSICAL_ADDR_OFFSET + 0x15160000)
#define PCMCIA1_8_CMN_WIN_BASE  	(PHYSICAL_ADDR_OFFSET + 0x151e0000)
#define PCMCIA0_16_CMN_WIN_BASE  	(PHYSICAL_ADDR_OFFSET + 0x15160000)
#define PCMCIA1_16_CMN_WIN_BASE  	(PHYSICAL_ADDR_OFFSET + 0x151e0000)

#define PCMCIA_CMN_WIN_SIZE     	0x00020000  		// 128 K

#define PCMCIA0_8_IO_WIN_BASE     (PHYSICAL_ADDR_OFFSET + 0x15100000)
#define PCMCIA1_8_IO_WIN_BASE     (PHYSICAL_ADDR_OFFSET + 0x151a0000)
#define PCMCIA0_16_IO_WIN_BASE    (PHYSICAL_ADDR_OFFSET + 0x15100000)
#define PCMCIA1_16_IO_WIN_BASE    (PHYSICAL_ADDR_OFFSET + 0x151a0000)

#define PCMCIA_IO_WIN_SIZE      	0x00020000  		// 128 K
#endif // R4101


//
// R4102 PCMCIA config
//
#ifdef R4102
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		0x11800000  // real physical address

// 32 Mbyte mapped in system address space for PCMCIA
//#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x02000000
#define PCMCIA_NUM_WINDOWS     		10	

#define PCMCIA0_16_ATTR_WIN_BASE 	0x11000000
#define PCMCIA0_8_ATTR_WIN_BASE 	0x11200000
#define PCMCIA1_16_ATTR_WIN_BASE 	0x11400000
#define PCMCIA1_8_ATTR_WIN_BASE 	0x11600000
#define PCMCIA_ATTR_WIN_SIZE    	0x00200000		// 2 MB

#define PCMCIA0_8_IO_WIN_BASE		0x11C00000
#define PCMCIA1_8_IO_WIN_BASE	  	0x11E00000
#define PCMCIA_IO_WIN_SIZE      	0x00200000 		// 2 MB

#define PCMCIA0_16_CMN_WIN_BASE  	0x12000000
#define PCMCIA0_8_CMN_WIN_BASE  	0x12800000
#define PCMCIA1_16_CMN_WIN_BASE  	0x13000000
#define PCMCIA1_8_CMN_WIN_BASE  	0x13800000
#define PCMCIA_CMN_WIN_SIZE     	0x00800000 		// 8 MB
#endif // R4102


//
// R4300 PCMCIA config  (PCMCIA currently not supported on R4300)
//
#if defined(R4300) || defined(IDT32364)
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		(SYSTEM_ASIC_REGS_BASE + 0xB000000)

#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x800000	// Only 8 Mbyte mapped in system address space
#define PCMCIA_NUM_WINDOWS     		10	

#define PCMCIA0_8_ATTR_WIN_BASE 	0x18000000
#define PCMCIA1_8_ATTR_WIN_BASE 	0x18800000
#define PCMCIA0_16_ATTR_WIN_BASE 	0x14000000
#define PCMCIA1_16_ATTR_WIN_BASE 	0x14800000
#define PCMCIA_ATTR_WIN_SIZE    	0x00200000		// 2 MB

#define PCMCIA0_8_CMN_WIN_BASE  	0x19000000
#define PCMCIA1_8_CMN_WIN_BASE  	0x19800000
#define PCMCIA0_16_CMN_WIN_BASE  	0x15000000
#define PCMCIA1_16_CMN_WIN_BASE  	0x15800000
#define PCMCIA_CMN_WIN_SIZE     	0x00800000  		// 8 MB

#define PCMCIA0_8_IO_WIN_BASE     	0x1A000000
#define PCMCIA1_8_IO_WIN_BASE     	0x1A800000

#define PCMCIA_IO_WIN_SIZE      	0x00200000  		// 2 MB
#endif // R4300


//
// PPC403 PCMCIA config
//
#ifdef PPC403
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		0x77000000  // REAL PHYSICAL ADDRESS

#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x800000	// Only 8 Mbyte mapped in system address space
#define PCMCIA_NUM_WINDOWS     		12

#define PCMCIA0_8_ATTR_WIN_BASE 	(0x72000000)
#define PCMCIA1_8_ATTR_WIN_BASE 	(0x72800000)
#define PCMCIA0_16_ATTR_WIN_BASE 	(0x70000000)
#define PCMCIA1_16_ATTR_WIN_BASE 	(0x70800000)
#define PCMCIA_ATTR_WIN_SIZE    	0x00800000		     // 8 MB

#define PCMCIA0_8_CMN_WIN_BASE  	(0x73000000)
#define PCMCIA1_8_CMN_WIN_BASE  	(0x73800000)
#define PCMCIA0_16_CMN_WIN_BASE  	(0x71000000)
#define PCMCIA1_16_CMN_WIN_BASE  	(0x71800000)
#define PCMCIA_CMN_WIN_SIZE     	0x00800000  		// 8 MB

#define PCMCIA0_8_IO_WIN_BASE     	(0x75000000)
#define PCMCIA1_8_IO_WIN_BASE     	(0x75800000)
#define PCMCIA0_16_IO_WIN_BASE     	(0x74000000)
#define PCMCIA1_16_IO_WIN_BASE     	(0x74800000)
#define PCMCIA_IO_WIN_SIZE      	0x00800000  		// 2 MB
#endif // PPC403


//
// PPC821 PCMCIA config
//
#ifdef PPC821
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		0x1B000000  // real physical address

#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x800000	// Only 8 Mbyte mapped in system address space
#define PCMCIA_NUM_WINDOWS     		12

#define PCMCIA0_8_ATTR_WIN_BASE 	(0x18000000)
#define PCMCIA1_8_ATTR_WIN_BASE 	(0x18800000)
#define PCMCIA0_16_ATTR_WIN_BASE 	(0x14000000)
#define PCMCIA1_16_ATTR_WIN_BASE 	(0x14800000)
#define PCMCIA_ATTR_WIN_SIZE    	0x00800000		     // 8 MB

#define PCMCIA0_8_CMN_WIN_BASE  	(0x19000000)
#define PCMCIA1_8_CMN_WIN_BASE  	(0x19800000)
#define PCMCIA0_16_CMN_WIN_BASE  	(0x15000000)
#define PCMCIA1_16_CMN_WIN_BASE  	(0x15800000)
#define PCMCIA_CMN_WIN_SIZE     	0x00800000  		// 8 MB

#define PCMCIA0_8_IO_WIN_BASE     	(0x1A000000)
#define PCMCIA1_8_IO_WIN_BASE     	(0x1A800000)
#define PCMCIA0_16_IO_WIN_BASE     	(0x16000000)
#define PCMCIA1_16_IO_WIN_BASE     	(0x16800000)


#define PCMCIA_IO_WIN_SIZE      	0x00800000  		// 2 MB
#endif // PPC821



//
// ARM720 PCMCIA config  (PCMCIA currently not supported on ARM720)
//
#ifdef ARM720
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		(SYSTEM_ASIC_REGS_BASE + 0x02000000)

#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x800000	// Only 8 Mbyte mapped in system address space
#define PCMCIA_NUM_WINDOWS     		10	

#define PCMCIA0_8_ATTR_WIN_BASE 	0x28000000
#define PCMCIA1_8_ATTR_WIN_BASE 	0x2A000000
#define PCMCIA0_16_ATTR_WIN_BASE 	0x28000000
#define PCMCIA1_16_ATTR_WIN_BASE 	0x2A000000
#define PCMCIA_ATTR_WIN_SIZE    	0x00800000		// 8 MB

#define PCMCIA0_8_CMN_WIN_BASE  	0x2C000000
#define PCMCIA1_8_CMN_WIN_BASE  	0x2E000000
#define PCMCIA0_16_CMN_WIN_BASE  	0x2C000000
#define PCMCIA1_16_CMN_WIN_BASE  	0x2E000000
#define PCMCIA_CMN_WIN_SIZE     	0x00800000  		// 8 MB

#define PCMCIA0_8_IO_WIN_BASE     	0x30000000
#define PCMCIA1_8_IO_WIN_BASE     	0x32000000

#define PCMCIA_IO_WIN_SIZE      	0x00200000  		// 2 MB
#endif // ARM720

//
// ARM920 PCMCIA config  (PCMCIA currently not supported on ARM920)
// This is just a cut and paste of ARM720 Caveat Emptor!!!
//
#ifdef ARM920
#define PCMCIA_BASE			    (SYSTEM_ASIC_REGS_BASE + 0x400)
#define PCMCIA_STATUS_BASE		(SYSTEM_ASIC_REGS_BASE + 0x02000000)

#define PCMCIA_MAPPED_SYSTEM_WINDOW_SIZE 0x800000	// Only 8 Mbyte mapped in system address space
#define PCMCIA_NUM_WINDOWS     		10	

#define PCMCIA0_8_ATTR_WIN_BASE 	0x28000000
#define PCMCIA1_8_ATTR_WIN_BASE 	0x2A000000
#define PCMCIA0_16_ATTR_WIN_BASE 	0x28000000
#define PCMCIA1_16_ATTR_WIN_BASE 	0x2A000000
#define PCMCIA_ATTR_WIN_SIZE    	0x00800000		// 8 MB

#define PCMCIA0_8_CMN_WIN_BASE  	0x2C000000
#define PCMCIA1_8_CMN_WIN_BASE  	0x2E000000
#define PCMCIA0_16_CMN_WIN_BASE  	0x2C000000
#define PCMCIA1_16_CMN_WIN_BASE  	0x2E000000
#define PCMCIA_CMN_WIN_SIZE     	0x00800000  		// 8 MB

#define PCMCIA0_8_IO_WIN_BASE     	0x30000000
#define PCMCIA1_8_IO_WIN_BASE     	0x32000000

#define PCMCIA_IO_WIN_SIZE      	0x00200000  		// 2 MB
#endif // ARM920

/*
 *  Bus State Controller Defines
 */

#define BCN_BCR1		0xFFFFFF60
#define BCN_BCR2		0xFFFFFF62

#define BCN_BCR1_DRAM_A2N3D	0x0010	// Area 2 normal, Area 3 DRAM
#define BCN_BCR1_A5PCM		0x0002	// Area 5 is PCMCIA access		
#define BCN_BCR1_A6PCM		0x0001	// Area 6 is PCMCIA access		

#define BCN_BCR2_A6SZ_16 	0x2000 
#define BCN_BCR2_A5SZ_8 	0x0400
#define BCN_BCR2_A4SZ_32	0x0300 
#define BCN_BCR2_A3SZ_32 	0x00C0
#define BCN_BCR2_A2SZ_32  	0x0030
#define BCN_BCR2_A2SZ_16  	0x0020  // Reserved Area on SH3, 16-bit bus
#define BCN_BCR2_A1SZ_32	0x000C

/*
 * Defines for SMC ethernet board. 
 */
//#define ETHERNET_BASE  (SYSTEM_ASIC_REGS_BASE + 0x3000)

// The low bit of this word is stored in the FPGA. If set to a 1, it will assert
// the RESET pin of the 91C94.
//#define SMC_HARD_RESET_REG (ETHERNET_BASE + 32)
    
// For debug ethernet routines, we set aside a chunk of memory for packet buffers
// if the IMGEBOOT variable is set (see config.bib).
//#define NOCACHE_BIT  0x20000000
//#define EDBG_PHYSICAL_MEMORY_START ((DMA_BUFFER_BASE&~NOCACHE_BIT)+0x30000)

#endif // _P2_H_