boot.asm

这是基于TI公司的DSP TMS320DM642而开发的TCP/UDP协议

      .title  "Flash bootup utility for DM642"
   	  .sect ".boot_load"
	  .global _boot
	  .ref _c_int00

CODE_START_ADDR   .equ    0x90000800  ;code start address in flash
CODE_START_IN_DSP .equ    0x00000400  ;L2 sram start address
CODE_SIZE         .equ    0x00030000  ;bootup code size in byte

;SDRAM_CODE_ADDR     .equ  0x80000000
;CODE_START_IN_FLASH .equ  0x90040000
;SDRAM_CODE_SIZE     .equ  0x00200000

;DATA_START_IN_DSP .equ    0x80000000  ;data memory start address in dsp
;DATA_START_ADDR   .equ    0x01410000  ;data start address in flash
;DATA_SIZE         .equ    0x00010000  ;the length of data segment

EMIF_GBLCTL       .equ    0x01800000  ;EMIF global control     
EMIF_CECTL1       .equ    0x01800004  ;address of EMIF CE1 control reg. 
EMIF_CECTL0       .equ    0x01800008  ;EMIF CE0control          
EMIF_CECTL2       .equ    0x01800010  ;EMIF CE0control        
EMIF_CELTL3       .equ    0x01800014  ;EMIF CE0control        
EMIF_SDCTL        .equ    0x01800018  ;SDRAM Control Reg.(SDCTL)     
EMIF_SDTIM        .equ    0x0180001c  ;SDRAM Timing Reg.(SDTIM) 
EMIF_SDEXT        .equ    0x01800020  ;SDRAM extension Reg.(SDEXT) 

EMIF_GBLCTL_V     .equ    0x00052078
EMIF_CECTL2_V     .equ    0x31e88611  ;
EMIF_CECTL1_V     .equ    0x31e88611  ;
EMIF_CECTL0_V     .equ    0xffffffd3  ;EMIF CE0control   ;0x30
EMIF_SDCTL_V      .equ    0x47227000  ;SDRAM Control Reg.(SDCTL)
EMIF_SDTIM_V      .equ    0x00000800  ;SDRAM Timing Reg.(SDTIM)

_boot:
            mvkl  EMIF_GBLCTL,A4    ;EMIF_GBLCTL address ->A4
      ||    mvkl  EMIF_GBLCTL_V,B4

            mvkh  EMIF_GBLCTL,A4
      ||    mvkh  EMIF_GBLCTL_V,B4

            stw   B4,*A4

            mvkl  EMIF_CECTL0,A4       ;EMIF_CECTL0 address ->A4
      ||    mvkl  EMIF_CECTL0_V,B4     ;

            mvkh  EMIF_CECTL0,A4
      ||    mvkh  EMIF_CECTL0_V,B4
      
            stw   B4,*A4  
            
            mvkl  EMIF_CECTL1,A4       ;EMIF_CECTL1 address ->A4
      ||    mvkl  EMIF_CECTL1_V,B4     ;

            mvkh  EMIF_CECTL1,A4
      ||    mvkh  EMIF_CECTL1_V,B4
      
            stw   B4,*A4                       
            
            mvkl  EMIF_CECTL2,A4       ;EMIF_CECTL1 address ->A4
      ||    mvkl  EMIF_CECTL2_V,B4     ;

            mvkh  EMIF_CECTL2,A4
      ||    mvkh  EMIF_CECTL2_V,B4
      
            stw   B4,*A4                       

      ||    mvkl  EMIF_SDCTL,A4       ;EMIF_SDCTRL address ->A4
      ||    mvkl  EMIF_SDCTL_V,B4     ;

            mvkh  EMIF_SDCTL,A4
      ||    mvkh  EMIF_SDCTL_V,B4     
      
            stw   B4,*A4               
             
      ||    mvkl  EMIF_SDTIM,A4      ;EMIF_SDRP address ->A4
      ||    mvkl  EMIF_SDTIM_V,B4    ;

            mvkh  EMIF_SDTIM,A4
      ||    mvkh  EMIF_SDTIM_V,B4
            
            stw   B4,*A4

            mvkl  CODE_START_IN_DSP,A4  ;ram start address ->A4
      ||    mvkl  CODE_START_ADDR,B4      ;flash start address ->B4

            mvkh  CODE_START_IN_DSP,A4
      ||    mvkh  CODE_START_ADDR,B4   
       

            zero  A1
_code_loop:
            ldb   *B4++,B5
            mvkl  CODE_SIZE,B6 ;B6 = CODE_SIZE

            add   1,A1,A1          ;A1+=1,inc outer counter
      ||    mvkh  CODE_SIZE,B6
       
            cmplt A1,B6,B0
            nop
            stb   B5,*A4++
      [B0]  b     _code_loop
            nop   5

;            mvkl  DATA_START_IN_DSP,A4  ;ram start address ->A4
;      ||    mvkl  DATA_START_ADDR,B4      ;flash start address ->B4

;            mvkh  DATA_START_IN_DSP,A4
;      ||    mvkh  DATA_START_ADDR,B4


;            zero  A1
            
;_data_loop:
;            ldb   *B4++,B5
;            mvkl  DATA_SIZE,B6 ;B6 = DATA_SIZE

;            add   1,A1,A1          ;A1+=1,inc outer counter
;      ||    mvkh  DATA_SIZE,B6
       
;            cmplt A1,B6,B0
;            nop   
;            stb   B5,*A4++
;      [B0]  b     _data_loop
;            nop   5    
            
            
;            mvkl  SDRAM_CODE_ADDR,A4  ;ram start address ->A4
;      ||    mvkl  CODE_START_IN_FLASH,B4      ;flash start address ->B4

;            mvkh  SDRAM_CODE_ADDR,A4
;      ||    mvkh  CODE_START_IN_FLASH,B4   


;            zero  A1
;_sdram_code_loop:
;            ldb   *B4++,B5
;            mvkl  SDRAM_CODE_SIZE,B6 ;B6 = DATA_SIZE

;            add   1,A1,A1          ;A1+=1,inc outer counter
;      ||    mvkh  SDRAM_CODE_SIZE,B6

;            cmplt A1,B6,B0
;            nop   
;            stb   B5,*A4++
;      [B0]  b     _sdram_code_loop
;            nop   5
            
            

            mvkl .S2 _c_int00, B0
            mvkh .S2 _c_int00, B0
            B    .S2 B0
            nop   5
.endfunc