12ce67x.mdf

该应用软件可以实现大多数单片机的仿真实验

LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   K:\PRODEV\VSM\pic12\eeprom\12ce67x.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  09/04/02
Modified: 07/01/04

*PROPERTIES,0    

*MODELDEFS,0    

*PARTLIST,2    
CPU,PIC12C67X,PIC12C67X,ADC_ACQUISITION_TIME=<ADC_ACQUISITION_TIME>,ADC_RCCLOCK_PERIOD=<ADC_RCCLOCK_PERIOD>,ADC_SAMPLE_DELAY=<ADC_SAMPLE_DELAY>,CFGWORD=<CFGWORD>,CLOCK=<CLOCK>,DBG_ADC_BREAK=<DBG_ADC_BREAK>,DBG_ADC_WARNINGS=<DBG_ADC_WARNINGS>,DBG_ADDRESSES=<DBG_ADDRESSES>,DBG_DUMP_CFGWORD=<DBG_DUMP_CFGWORD>,DBG_GENERATE_CLKOUT=<DBG_GENERATE_CLKOUT>,DBG_RANDOM_DMEM=<DBG_RANDOM_DMEM>,DBG_RANDOM_PMEM=<DBG_RANDOM_PMEM>,DBG_RESET=<DBG_RESET>,DBG_STACK=<DBG_STACK>,DBG_STARTUP_DELAY=<DBG_STARTUP_DELAY>,DBG_UNIMPLEMENTED_MEMORY=<DBG_UNIMPLEMENTED_MEMORY>,DBG_UNIMPLEMENTED_OPCODES=<DBG_UNIMPLEMENTED_OPCODES>,DBG_WAKEUP_DELAY=<DBG_WAKEUP_DELAY>,MODDLL=<MODDLL>,PORTTDHL=<PORTTDHL>,PORTTDLH=<PORTTDLH>,PRIMITIVE=DIGITAL,PRIMTYPE=<PRIMTYPE>,PROGRAM=<PROGRAM>,WDT_PERIOD=<WDT_PERIOD>
EEPROM,EEPROM,EEPROM,ADDRWIDTH=4,ALWAYS_ACK_DATA=1,BLKADDRMASK=0x00,BLKADDRSHIFT=0,BYTETIMING=0,CMDWIDTH=8,DATAWIDTH=8,DVCADDRMASK=0x00,DVCADDRSHIFT=0,INCRADDR=0,LOG_ACKS=<DBG_I2CMEM_LOG>,LOG_ADDRS=<DBG_I2CMEM_LOG>,LOG_CMDS=<DBG_I2CMEM_LOG>,LOG_DATA=<DBG_I2CMEM_LOG>,LOG_OTHER=<DBG_I2CMEM_LOG>,LOG_STARTSTOP=<DBG_I2CMEM_LOG>,LOG_SWP=<DBG_I2CMEM_LOG>,MEMSIZE=16,MODDATA="16,255",MODDLL=I2CMEM.DLL,PRIMITIVE=DIGITAL,TD_BUSFREE=1.3u,TD_CLK_ACK=100n,TD_CLK_ENDDATA=100n,TD_CLK_HIGH=600n,TD_CLK_LOW=1.3u,TD_CLK_SDO=900n,TD_CLK_UNACK=100n,TD_DATA_SETUP=100n,TD_RSTART_SETUP=600n,TD_START_HOLD=600n,TD_STOP_SETUP=600n,TD_WP_HOLD=0,TD_WP_SETUP=0,TD_WRITE=1m,WARN_ADDRS=<DBG_I2CMEM_WARN>,WARN_CMDS=<DBG_I2CMEM_WARN>,WARN_OTHER=<DBG_I2CMEM_WARN>,WARN_TIMING=<DBG_I2CMEM_WARN>,WPAGESIZE=1,WPHIGH=0x0007,WPLOW=0x0000

*NETLIST,10   
#00000,2
EEPROM,IP,SCK
CPU,OP,SCL

#00001,2
EEPROM,IO,SDA
CPU,IO,SDA

GP5/OSC1,2
GP5/OSC1,GT
CPU,IO,GP5/OSC1

GP4/OSC2/AN3,2
GP4/OSC2/AN3,GT
CPU,IO,GP4/OSC2/AN3

GP3/$MCLR$,2
GP3/$MCLR$,GT
CPU,IO,GP3/$MCLR$

GP0/AN0,2
GP0/AN0,GT
CPU,IO,GP0/AN0

GP1/AN1/VREF,2
GP1/AN1/VREF,GT
CPU,IO,GP1/AN1/VREF

GP2/T0CKI/INT/AN2,2
GP2/T0CKI/INT/AN2,GT
CPU,IO,GP2/T0CKI/INT/AN2

VDD,2
VDD,GT
CPU,PP,VDD

VSS,2
VSS,GT
CPU,PP,VSS

*GATES,0