📄 m104def.inc
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;***************************************************************************
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
;*
;* Number : AVR000
;* File Name : "m104def.inc"
;* Title : Register/Bit Definitions for the ATmega104
;* Date : January 25th, 2000
;* Version : 1.0
;* Support telephone : +47 72 88 43 88 (ATMEL Norway)
;* Support fax : +47 72 88 43 99 (ATMEL Norway)
;* Support E-mail : support@atmel.no
;* Target MCU : ATmega104
;*
;* DESCRIPTION
;* When including this file in the assembly program file, all I/O register
;* names and I/O register bit names appearing in the data book can be used.
;* In addition, the six registers forming the three data pointers X, Y and
;* Z have been assigned names XL - ZH. Highest RAM address for Internal
;* SRAM is also defined
;*
;* The Register names are represented by their hexadecimal address.
;*
;* The Register Bit names are represented by their bit number (0-7).
;*
;* Please observe the difference in using the bit names with instructions
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
;* (skip if bit in register set/cleared). The following example illustrates
;* this:
;*
;* in r16,PORTB ;read PORTB latch
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
;* out PORTB,r16 ;output to PORTB
;*
;* in r16,TIFR ;read the Timer Interrupt Flag Register
;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
;* rjmp TOV0_is_set ;jump if set
;* ... ;otherwise do something else
;***************************************************************************
;$Author: rpedersen $
;$Date: 2001/05/21 14:28:13 $
;$Revision: 1.27 $
;$Source: /pro/common/simfiles/RCS/m104def.inc,v $
;**** Specify Device ****
;.device ATmega104
;*****************************************************************************
; I/O Register Definitions
;*****************************************************************************
;**** Memory Mapped I/O Register Definitions ($FF-$60) ****
.equ UCSR1C = $9D
.equ UDR1 = $9C
.equ UCSR1A = $9B
.equ UCSR1B = $9A
.equ UBRR1L = $99
.equ UBRR1H = $98
.equ UCSR0C = $95
.equ UBRR0H = $90
.equ TCCR3C = $8C
.equ TCCR3A = $8B
.equ TCCR3B = $8A
.equ TCNT3H = $89
.equ TCNT3L = $88
.equ OCR3AH = $87
.equ OCR3AL = $86
.equ OCR3BH = $85
.equ OCR3BL = $84
.equ OCR3CH = $83
.equ OCR3CL = $82
.equ ICR3H = $81
.equ ICR3L = $80
.equ ETIMSK = $7D
.equ ETIFR = $7C
.equ TCCR1C = $7A
.equ OCR1CH = $79
.equ OCR1CL = $78
.equ TWCR = $74
.equ TWDR = $73
.equ TWAR = $72
.equ TWSR = $71
.equ TWBR = $70
.equ OSCCAL = $6F
.equ XMCRA = $6D
.equ XMCRB = $6C
.equ EICRA = $6A
.equ SPMCSR = $68
.equ SPMCR = $68 ; old name for SPMCSR
.equ PORTG = $65
.equ DDRG = $64
.equ PING = $63
.equ PORTF = $62
.equ DDRF = $61
;**** I/O Register Definitions ($3F-$00) ****
.equ SREG = $3F
.equ SPH = $3E
.equ SPL = $3D
.equ XDIV = $3C
.equ RAMPZ = $3B
.equ EICRB = $3A
.equ EIMSK = $39
.equ GIMSK = $39 ; old name for EIMSK
.equ GICR = $39 ; old name for EIMSK
.equ EIFR = $38
.equ GIFR = $38 ; old name for EIFR
.equ TIMSK = $37
.equ TIFR = $36
.equ MCUCR = $35
.equ MCUCSR = $34
.equ TCCR0 = $33
.equ TCNT0 = $32
.equ OCR0 = $31
.equ ASSR = $30
.equ TCCR1A = $2F
.equ TCCR1B = $2E
.equ TCNT1H = $2D
.equ TCNT1L = $2C
.equ OCR1AH = $2B
.equ OCR1AL = $2A
.equ OCR1BH = $29
.equ OCR1BL = $28
.equ ICR1H = $27
.equ ICR1L = $26
.equ TCCR2 = $25
.equ TCNT2 = $24
.equ OCR2 = $23
.equ OCDR = $22 ; New
.equ WDTCR = $21
.equ SFIOR = $20 ; New
.equ EEARH = $1F
.equ EEARL = $1E
.equ EEDR = $1D
.equ EECR = $1C
.equ PORTA = $1B
.equ DDRA = $1A
.equ PINA = $19
.equ PORTB = $18
.equ DDRB = $17
.equ PINB = $16
.equ PORTC = $15
.equ DDRC = $14 ; New
.equ PINC = $13 ; New
.equ PORTD = $12
.equ DDRD = $11
.equ PIND = $10
.equ SPDR = $0F
.equ SPSR = $0E
.equ SPCR = $0D
.equ UDR0 = $0C
.equ UCSR0A = $0B
.equ UCSR0B = $0A
.equ UBRR0L = $09
.equ ACSR = $08
.equ ADMUX = $07
.equ ADCSR = $06
.equ ADCH = $05
.equ ADCL = $04
.equ PORTE = $03
.equ DDRE = $02
.equ PINE = $01
.equ PINF = $00
;*****************************************************************************
; Bit Definitions
;*****************************************************************************
;**** MCU Control ****
.equ SRE = 7 ; MCUCR
.equ SRW10 = 6
.equ SE = 5
.equ SM1 = 4
.equ SM0 = 3
.equ SM2 = 2
.equ IVSEL = 1
.equ IVCE = 0
.equ JTD = 7 ; MCUCSR
.equ JTRF = 4
.equ WDRF = 3
.equ BORF = 2
.equ EXTRF = 1
.equ PORF = 0
.equ SRL2 =6 ; XMCRA
.equ SRL1 =5
.equ SRL0 =4
.equ SRW01 =3
.equ SRW00 =2
.equ SRW11 =1
.equ XMBK = 7 ; XMCRB
.equ XMM2 = 2
.equ XMM1 = 1
.equ XMM0 = 0
.equ SPMIE =7 ; SPMCSR
.equ ASB =6 ; backwards compatiblity
.equ ASRE =4 ; backwards compatiblity
.equ RWWSB =6
.equ RWWSRE =4
.equ BLBSET =3
.equ PGWRT =2
.equ PGERS =1
.equ SPMEN =0
.equ IDRD = 7 ; OCDR
.equ OCDR6 = 6
.equ OCDR5 = 5
.equ OCDR4 = 4
.equ OCDR3 = 3
.equ OCDR2 = 2
.equ OCDR1 = 1
.equ OCDR0 = 0
.equ XDIVEN = 7 ; XDIV
.equ XDIV6 = 6
.equ XDIV5 = 5
.equ XDIV4 = 4
.equ XDIV3 = 3
.equ XDIV2 = 2
.equ XDIV1 = 1
.equ XDIV0 = 0
.equ TSM = 7 ; SFIOR
.equ ADHSM = 4
.equ ACME = 3
.equ PUD = 2
.equ PSR0 = 1
.equ PSR1 = 0
.equ PSR2 = 0
.equ PSR3 = 0
.equ PSR321 = 0
;**** Analog to Digital Converter ****
.equ ADEN = 7 ; ADCSR
.equ ADSC = 6
.equ ADFR = 5
.equ ADIF = 4
.equ ADIE = 3
.equ ADPS2 = 2
.equ ADPS1 = 1
.equ ADPS0 = 0
.equ REFS1 =7 ; ADMUX
.equ REFS0 =6
.equ ADLAR =5
.equ MUX4 =4
.equ MUX3 =3
.equ MUX2 =2
.equ MUX1 =1
.equ MUX0 =0
;**** Analog Comparator ****
.equ ACD = 7 ; ACSR
.equ ACBG = 6
.equ ACO = 5
.equ ACI = 4
.equ ACIE = 3
.equ ACIC = 2
.equ ACIS1 = 1
.equ ACIS0 = 0
;**** External Interrupts ****
.equ INT7 = 7 ; EIMSK
.equ INT6 = 6
.equ INT5 = 5
.equ INT4 = 4
.equ INT3 = 3
.equ INT2 = 2
.equ INT1 = 1
.equ INT0 = 0
.equ INTF7 = 7 ; EIFR
.equ INTF6 = 6
.equ INTF5 = 5
.equ INTF4 = 4
.equ INTF3 = 3
.equ INTF2 = 2
.equ INTF1 = 1
.equ INTF0 = 0
.equ ISC71 = 7 ; EICRB
.equ ISC70 = 6
.equ ISC61 = 5
.equ ISC60 = 4
.equ ISC51 = 3
.equ ISC50 = 2
.equ ISC41 = 1
.equ ISC40 = 0
.equ ISC31 = 7 ; EICRA
.equ ISC30 = 6
.equ ISC21 = 5
.equ ISC20 = 4
.equ ISC11 = 3
.equ ISC10 = 2
.equ ISC01 = 1
.equ ISC00 = 0
;**** Timer Interrupts ****
.equ OCIE2 = 7 ; TIMSK
.equ TOIE2 = 6
.equ TICIE1 = 5
.equ OCIE1A = 4
.equ OCIE1B = 3
.equ TOIE1 = 2
.equ OCIE0 = 1
.equ TOIE0 = 0
.equ TICIE3 = 5 ; ETIMSK
.equ OCIE3A = 4
.equ OCIE3B = 3
.equ TOIE3 = 2
.equ OCIE3C = 1
.equ OCIE1C = 0
.equ OCF2 = 7 ; TIFR
.equ TOV2 = 6
.equ ICF1 = 5
.equ OCF1A = 4
.equ OCF1B = 3
.equ TOV1 = 2
.equ OCF0 = 1
.equ TOV0 = 0
.equ ICF3 = 5 ; ETIFR
.equ OCF3A = 4
.equ OCF3B = 3
.equ TOV3 = 2
.equ OCF3C = 1
.equ OCF1C = 0
;**** Asynchronous Timer ****
.equ AS0 = 3 ; ASSR
.equ TCN0UB = 2
.equ OCR0UB = 1
.equ TCR0UB = 0
;**** Timer 0 ****
.equ FOC0 = 7 ; TCCR0
.equ PWM0 = 6
.equ COM01 = 5
.equ COM00 = 4
.equ CTC0 = 3
.equ CS02 = 2
.equ CS01 = 1
.equ CS00 = 0
;**** Timer 1 ****
.equ COM1A1 = 7 ; TCCR1A
.equ COM1A0 = 6
.equ COM1B1 = 5
.equ COM1B0 = 4
.equ COM1C1 = 3
.equ COM1C0 = 2
.equ PWM11 = 1 ; OBSOLETE! Use WGM11
.equ PWM10 = 0 ; OBSOLETE! Use WGM10
.equ WGM11 = 1
.equ WGM10 = 0
.equ ICNC1 = 7 ; TCCR1B
.equ ICES1 = 6
.equ CTC11 = 4 ; OBSOLETE! Use WGM13
.equ CTC10 = 3 ; OBSOLETE! Use WGM12
.equ WGM13 = 4
.equ WGM12 = 3
.equ CS12 = 2
.equ CS11 = 1
.equ CS10 = 0
.equ FOC1A = 7 ; TCCR1C
.equ FOC1B = 6
.equ FOC1C = 5
;**** Timer 2 ****
.equ FOC2 = 7 ; TCCR2
.equ PWM2 = 6
.equ COM21 = 5
.equ COM20 = 4
.equ CTC2 = 3
.equ CS22 = 2
.equ CS21 = 1
.equ CS20 = 0
;**** Timer 3 ****
.equ COM3A1 = 7 ; TCCR3A
.equ COM3A0 = 6
.equ COM3B1 = 5
.equ COM3B0 = 4
.equ COM3C1 = 3
.equ COM3C0 = 2
.equ PWM31 = 1 ; OBSOLETE! Use WGM31
.equ PWM30 = 0 ; OBSOLETE! Use WGM30
.equ WGM31 = 1
.equ WGM30 = 0
.equ ICNC3 = 7 ; TCCR3B
.equ ICES3 = 6
.equ CTC31 = 4 ; OBSOLETE! Use WGM33
.equ CTC30 = 3 ; OBSOLETE! Use WGM32
.equ WGM33 = 4
.equ WGM32 = 3
.equ CS32 = 2
.equ CS31 = 1
.equ CS30 = 0
.equ FOC3A = 7 ; TCCR3C
.equ FOC3B = 6
.equ FOC3C = 5
;**** Watchdog Timer ****
.equ WDCE = 4 ; WDTCR
.equ WDTOE = 4 ; For Mega103 compability
.equ WDE = 3
.equ WDP2 = 2
.equ WDP1 = 1
.equ WDP0 = 0
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