📄 p18f2320.inc
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; P18F2320.INC Standard Header File, Version 0.1 Microchip Technology, Inc.
NOLIST
; This header file defines configurations, registers, and other useful
; bits of information for the PIC18F2320 microcontroller. These names
; are taken to match the data sheets as closely as possible.
; Note that the processor must be selected before this file is
; included. The processor may be selected the following ways:
; 1. Command line switch:
; C:\ MPASM MYFILE.ASM /PIC18F2320
; 2. LIST directive in the source file
; LIST P=PIC18F2320
; 3. Processor Type entry in the MPASM full-screen interface
; 4. Setting the processor in the MPLAB Project Dialog
;=======================================================================
;
; Revision History
;
;=======================================================================
;Rev: Date: Details: Who:
;0.10 07 Dec 2001 Initial revision BD
;0.11 22 Mar 2002 ECCP registers revised BD
;0.12 16 Apr 2002 Configuration bit MCLRE moved from 2L to 3H BD
;0.13 22 Apr 2002 T0CON<T0PS3> changed back to T0CON<PSA> BD
;0.14 09 May 2002 Removed PWM1CON and ECCPAS registers BD
; ECCP1CON changed to CCP1CON
;0.15 5 May 2002 _OSO_ON_1H changed to _IESO_ON_1H BD
; _MCLRE_ON_2L moved/changed to _MCLRE_ON_3H
;
;0.16 24 May 2002 OSCCON<OSTS> bit name corrected BD
; OSCCON register name above bit equates fixed
; T1CON<T1RUN/NOT_T1RUN> added
; _MCLRE_ON_3H moved to correct register and renamed (again)
;0.17 30 May 2002 _PBAD_DIG_3H had wrong bit cleared BD
;0.18 13 Jun 2002 LVDCON,IRVST added to LVDCON BD
;0.19 09/26/02 Include both names SWDTE and SWDTEN pas
;
;0.20 27 Sep 2002 Add IOFS bit name to OSCCON register BD
; Add ECIO, RCIO, INTIO1, INTIO2 bits to Config Reg 1H
; Add DEBUG bits to Config Reg 4L
;0.21 21 Jan 2003 Changed _MCLRE_OFF_3H from 0xEF to 0x7F BD
;
;0.22 1 Oct 2003 Bit names changed BD
; LVVn to LVDLn IVRST to IRVST
; FSCMEN to FSCM
; Bit names removed - EPWM1M1,EPWM1M0,EDC1B1,
; EDC1B0,ECCP1M3,ECCP1M2,ECCP1M1,ECCP1M0,
; CVREF,CVRSS
; Removed redundant bit names
; RCIO6 use RCIO INTIO7 use INTIO1
; ECIO6 use ECIO INTIO67 use INTIO2
; BKBUG use DEBUG SWDTE use SWDTEN
; T0IE use TMR0IE INT0E use INT0IE
; T0IF use TMR0IF INT0F use INT0IE
; BGST use IRVST T1INSYNC use T1SYNC
; TXD8 use TX9D T3INSYNC use T3SYNC
; TX8_9 use TX9 NOT_TX8 use TX9
; RC9 use RX9 NOT_RC8 use RX9
; RC8_9 use RX9 RCD8 use RX9D
; INT2P use INT2IP INT1P use INT1IP
; INT2E use INT2IE INT1E use INT1IE
; INT2F use INT2IF INT1F use INT1IF
; Added equates for PIC16 Compatability
; ADRES, INTF, INTE, CCPnX, CCPnY
; General clean-up (removed some comments)
; Corrected RAM space definitions
;
;0.23 30 Mar 2004 References to RE3 removed, badram adjusted BD
;=======================================================================
;
; Verify Processor
;
;=======================================================================
IFNDEF __18F2320
MESSG "Processor-header file mismatch. Verify selected processor."
ENDIF
;=======================================================================
; 18Fxxx Family EQUates
;=======================================================================
FSR0 EQU 0
FSR1 EQU 1
FSR2 EQU 2
FAST EQU 1
W EQU 0
A EQU 0
ACCESS EQU 0
BANKED EQU 1
;=======================================================================
; 16Cxxx/17Cxxx Substitutions
;=======================================================================
#define DDRA TRISA ; PIC17Cxxx SFR substitution
#define DDRB TRISB ; PIC17Cxxx SFR substitution
#define DDRC TRISC ; PIC17Cxxx SFR substitution
#define ADRES ADRESH ; PIC16 SFR substitution
#define INTE INT0IE ; PIC16 bit substitution
#define INTF INT0IF ; PIC16 bit substitution
#define CCP1X DC1B1 ; PIC16 bit substitution
#define CCP1Y DC1B0 ; PIC16 bit substitution
#define CCP2X DC2B1 ; PIC16 bit substitution
#define CCP2Y DC2B0 ; PIC16 bit substitution
#define SCS SCS0 ; PIC18 bit substitution
;=======================================================================
;
; Register Definitions
;
;=======================================================================
;----- Register Files --------------------------------------------------
TOSU EQU H'0FFF'
TOSH EQU H'0FFE'
TOSL EQU H'0FFD'
STKPTR EQU H'0FFC'
PCLATU EQU H'0FFB'
PCLATH EQU H'0FFA'
PCL EQU H'0FF9'
TBLPTRU EQU H'0FF8'
TBLPTRH EQU H'0FF7'
TBLPTRL EQU H'0FF6'
TABLAT EQU H'0FF5'
PRODH EQU H'0FF4'
PRODL EQU H'0FF3'
INTCON EQU H'0FF2'
INTCON2 EQU H'0FF1'
INTCON3 EQU H'0FF0'
INDF0 EQU H'0FEF'
POSTINC0 EQU H'0FEE'
POSTDEC0 EQU H'0FED'
PREINC0 EQU H'0FEC'
PLUSW0 EQU H'0FEB'
FSR0H EQU H'0FEA'
FSR0L EQU H'0FE9'
WREG EQU H'0FE8'
INDF1 EQU H'0FE7'
POSTINC1 EQU H'0FE6'
POSTDEC1 EQU H'0FE5'
PREINC1 EQU H'0FE4'
PLUSW1 EQU H'0FE3'
FSR1H EQU H'0FE2'
FSR1L EQU H'0FE1'
BSR EQU H'0FE0'
INDF2 EQU H'0FDF'
POSTINC2 EQU H'0FDE'
POSTDEC2 EQU H'0FDD'
PREINC2 EQU H'0FDC'
PLUSW2 EQU H'0FDB'
FSR2H EQU H'0FDA'
FSR2L EQU H'0FD9'
STATUS EQU H'0FD8'
TMR0H EQU H'0FD7'
TMR0L EQU H'0FD6'
T0CON EQU H'0FD5'
; reserved H'0FD4'
OSCCON EQU H'0FD3'
LVDCON EQU H'0FD2'
WDTCON EQU H'0FD1'
RCON EQU H'0FD0'
TMR1H EQU H'0FCF'
TMR1L EQU H'0FCE'
T1CON EQU H'0FCD'
TMR2 EQU H'0FCC'
PR2 EQU H'0FCB'
T2CON EQU H'0FCA'
SSPBUF EQU H'0FC9'
SSPADD EQU H'0FC8'
SSPSTAT EQU H'0FC7'
SSPCON1 EQU H'0FC6'
SSPCON2 EQU H'0FC5'
ADRESH EQU H'0FC4'
ADRESL EQU H'0FC3'
ADCON0 EQU H'0FC2'
ADCON1 EQU H'0FC1'
ADCON2 EQU H'0FC0'
CCPR1H EQU H'0FBF'
CCPR1L EQU H'0FBE'
CCP1CON EQU H'0FBD'
CCPR2H EQU H'0FBC'
CCPR2L EQU H'0FBB'
CCP2CON EQU H'0FBA'
; reserved EQU H'0FB9'
; reserved EQU H'0FB8'
; reserved EQU H'0FB7'
; reserved EQU H'0FB6'
CVRCON EQU H'0FB5'
CMCON EQU H'0FB4'
TMR3H EQU H'0FB3'
TMR3L EQU H'0FB2'
T3CON EQU H'0FB1'
; reserved EQU H'0FB0'
SPBRG EQU H'0FAF'
RCREG EQU H'0FAE'
TXREG EQU H'0FAD'
TXSTA EQU H'0FAC'
RCSTA EQU H'0FAB'
; reserved EQU H'0FAA'
EEADR EQU H'0FA9'
EEDATA EQU H'0FA8'
EECON2 EQU H'0FA7'
EECON1 EQU H'0FA6'
; reserved EQU H'0FB5'
; reserved EQU H'0FB4'
; reserved EQU H'0FB3'
IPR2 EQU H'0FA2'
PIR2 EQU H'0FA1'
PIE2 EQU H'0FA0'
IPR1 EQU H'0F9F'
PIR1 EQU H'0F9E'
PIE1 EQU H'0F9D'
OSCTUNE EQU H'0F9B'
; reserved EQU H'0F9A'
; reserved EQU H'0F99'
; reserved EQU H'0F98'
; reserved EQU H'0F97'
; reserved EQU H'0F96'
; reserved EQU H'0F95'
TRISC EQU H'0F94'
TRISB EQU H'0F93'
TRISA EQU H'0F92'
; reserved EQU H'0F91'
; reserved EQU H'0F90'
; reserved EQU H'0F8F'
; reserved EQU H'0F8E'
; reserved EQU H'0F8D'
; reserved EQU H'0F8C'
LATC EQU H'0F8B'
LATB EQU H'0F8A'
LATA EQU H'0F89'
; reserved EQU H'0F88'
; reserved EQU H'0F87'
; reserved EQU H'0F86'
; reserved EQU H'0F85'
; reserved EQU H'0F84'
; reserved EQU H'0F83'
PORTC EQU H'0F82'
PORTB EQU H'0F81'
PORTA EQU H'0F80'
;----- STKPTR Bits -----------------------------------------------------
STKFUL EQU H'0007'
STKUNF EQU H'0006'
;----- INTCON Bits -----------------------------------------------------
GIE EQU H'0007'
GIEH EQU H'0007'
PEIE EQU H'0006'
GIEL EQU H'0006'
TMR0IE EQU H'0005'
INT0IE EQU H'0004'
RBIE EQU H'0003'
TMR0IF EQU H'0002'
INT0IF EQU H'0001'
RBIF EQU H'0000'
;----- INTCON2 Bits ----------------------------------------------------
NOT_RBPU EQU H'0007'
RBPU EQU H'0007'
INTEDG0 EQU H'0006'
INTEDG1 EQU H'0005'
INTEDG2 EQU H'0004'
TMR0IP EQU H'0002'
T0IP EQU H'0002'
RBIP EQU H'0000'
;----- INTCON3 Bits ----------------------------------------------------
INT2IP EQU H'0007'
INT1IP EQU H'0006'
INT2IE EQU H'0004'
INT1IE EQU H'0003'
INT2IF EQU H'0001'
INT1IF EQU H'0000'
;----- STATUS Bits -----------------------------------------------------
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