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PDC5 EQU H'0005'
PDC4 EQU H'0004'
PDC3 EQU H'0003'
PDC2 EQU H'0002'
PDC1 EQU H'0001'
PDC0 EQU H'0000'
;----- ECCPAS Bits -----------------------------------------------------
ECCPASE EQU H'0007'
ECCPAS2 EQU H'0006'
ECCPAS1 EQU H'0005'
ECCPAS0 EQU H'0004'
PSSAC1 EQU H'0003'
PSSAC0 EQU H'0002'
PSSBD1 EQU H'0001'
PSSBD0 EQU H'0000'
;----- T3CON Bits ------------------------------------------------------
RD16 EQU H'0007'
T3CCP2 EQU H'0006'
T3CKPS1 EQU H'0005'
T3CKPS0 EQU H'0004'
T3CCP1 EQU H'0003'
NOT_T3SYNC EQU H'0002'
T3SYNC EQU H'0002'
TMR3CS EQU H'0001'
TMR3ON EQU H'0000'
;----- TXSTA Bits ------------------------------------------------------
CSRC EQU H'0007'
TX9 EQU H'0006'
TXEN EQU H'0005'
SYNC EQU H'0004'
SENDB EQU H'0003'
BRGH EQU H'0002'
TRMT EQU H'0001'
TX9D EQU H'0000'
;----- RCSTA Bits ------------------------------------------------------
SPEN EQU H'0007'
RX9 EQU H'0006'
SREN EQU H'0005'
CREN EQU H'0004'
ADDEN EQU H'0003'
FERR EQU H'0002'
OERR EQU H'0001'
RX9D EQU H'0000'
;----- BAUDCTL Bits ------------------------------------------------------
RCIDL EQU H'0006'
SCKP EQU H'0004'
BRG16 EQU H'0003'
WUE EQU H'0001'
ABDEN EQU H'0000'
;----- EECON1 Bits -----------------------------------------------------
EEPGD EQU H'0007'
CFGS EQU H'0006'
FREE EQU H'0004'
WRERR EQU H'0003'
WREN EQU H'0002'
WR EQU H'0001'
RD EQU H'0000'
;----- IPR2 Bits -------------------------------------------------------
OSCFIP EQU H'0007'
EEIP EQU H'0004'
LVDIP EQU H'0002'
TMR3IP EQU H'0001'
;----- PIR2 Bits -------------------------------------------------------
OSCFIF EQU H'0007'
EEIF EQU H'0004'
LVDIF EQU H'0002'
TMR3IF EQU H'0001'
;----- PIE2 Bits -------------------------------------------------------
OSCFIE EQU H'0007'
EEIE EQU H'0004'
LVDIE EQU H'0002'
TMR3IE EQU H'0001'
;----- IPR1 Bits -------------------------------------------------------
ADIP EQU H'0006'
RCIP EQU H'0005'
TXIP EQU H'0004'
CCP1IP EQU H'0002'
TMR2IP EQU H'0001'
TMR1IP EQU H'0000'
;----- PIR1 Bits -------------------------------------------------------
ADIF EQU H'0006'
RCIF EQU H'0005'
TXIF EQU H'0004'
CCP1IF EQU H'0002'
TMR2IF EQU H'0001'
TMR1IF EQU H'0000'
;----- PIE1 Bits -------------------------------------------------------
ADIE EQU H'0006'
RCIE EQU H'0005'
TXIE EQU H'0004'
CCP1IE EQU H'0002'
TMR2IE EQU H'0001'
TMR1IE EQU H'0000'
;----- OSCTUNE Bits ----------------------------------------------------
TUN5 EQU H'0005'
TUN4 EQU H'0004'
TUN3 EQU H'0003'
TUN2 EQU H'0002'
TUN1 EQU H'0001'
TUN0 EQU H'0000'
;=======================================================================
;
; I/O Pin Name Definitions
;
;=======================================================================
;----- PORTA -----------------------------------------------------------
RA0 EQU 0
AN0 EQU 0
RA1 EQU 1
AN1 EQU 1
LVDIN EQU 1
RA2 EQU 2
AN2 EQU 2
VREFM EQU 2
RA3 EQU 3
AN3 EQU 3
VREFP EQU 3
RA4 EQU 4
T0CKI EQU 4
RA5 EQU 5
RA6 EQU 6
OSC2 EQU 6
CLKO EQU 6
RA7 EQU 7
OSC1 EQU 7
CLKI EQU 7
;----- PORTB -----------------------------------------------------------
RB0 EQU 0
INT0 EQU 0
AN4 EQU 0
RB1 EQU 1
INT1 EQU 1
AN5 EQU 1
TX EQU 1
CK EQU 1
RB2 EQU 2
INT2 EQU 2
P1B EQU 2
RB3 EQU 3
CCP1 EQU 3
P1A EQU 3
RB4 EQU 4
KBI0 EQU 4
AN6 EQU 4
RX EQU 4
RB5 EQU 5
KBI1 EQU 5
PGM EQU 5
RB6 EQU 6
KBI2 EQU 6
PGC EQU 6
T1OSO EQU 6
T1CKI EQU 6
P1C EQU 7
RB7 EQU 7
KBI3 EQU 7
T1OSI EQU 7
PGD EQU 7
P1D EQU 7
;=======================================================================
;
; RAM Definition
;
;=======================================================================
__MAXRAM H'FFF'
__BADRAM H'100'-H'F7F'
__BADRAM H'F82'-H'F88',H'F8B'-H'F91',H'F94'-H'F9A',H'F9C'
__BADRAM H'FA3'-H'FA5',H'FB4'-H'FB5',H'FB8'-H'FBC'
__BADRAM H'FC5'-H'FC9',H'FD4'
;=======================================================================
;
; ID Location Registers
;
; The following is an assignment of address values for all of the
; ID Location registers for the purpose of table reads and writes,
; and for device programming.
_IDLOC0 EQU H'200000'
_IDLOC1 EQU H'200001'
_IDLOC2 EQU H'200002'
_IDLOC3 EQU H'200003'
_IDLOC4 EQU H'200004'
_IDLOC5 EQU H'200005'
_IDLOC6 EQU H'200006'
_IDLOC7 EQU H'200007'
; To use the IDLOC registers, place the following lines in your source
; code in the following format, and change <expression> as desired.
; These lines are currently commented out here and each __IDLOCS line
; should have the preceding semicolon removed when pasted into your
; source code.
;
; <expression> should take the form of B'1111bbbb' or H'Fn'
; where b = user defined bit, or n = user defined nibble.
; Program IDLOC registers
; __IDLOCS _IDLOC0, <expression>
; __IDLOCS _IDLOC1, <expression>
; __IDLOCS _IDLOC2, <expression>
; __IDLOCS _IDLOC3, <expression>
; __IDLOCS _IDLOC4, <expression>
; __IDLOCS _IDLOC5, <expression>
; __IDLOCS _IDLOC6, <expression>
; __IDLOCS _IDLOC7, <expression>
;=======================================================================
;
; Configuration Bits
;
; The following is an assignment of address values for all of the
; configuration registers for the purpose of table reads and writes,
; and for programming configuration words.
_CONFIG1H EQU H'300001'
_CONFIG2L EQU H'300002'
_CONFIG2H EQU H'300003'
_CONFIG3H EQU H'300005'
_CONFIG4L EQU H'300006'
_CONFIG5L EQU H'300008'
_CONFIG5H EQU H'300009'
_CONFIG6L EQU H'30000A'
_CONFIG6H EQU H'30000B'
_CONFIG7L EQU H'30000C'
_CONFIG7H EQU H'30000D'
; To embed the Configuration Bits in your source code, paste the
; following lines into your source code in the following format,
; and change the configuration value to the desired setting (such
; as WDT_OFF to WDT_ON).
; These lines are commented out - each __CONFIG line should have the
; preceding semicolon (;) removed when pasted into your source code.
; __CONFIG _CONFIG1H, _IESO_ON_1H & _FSCM_OFF_1H & _RC_OSC_1H
; __CONFIG _CONFIG2L, _PWRT_ON_2L & _BOR_OFF_2L & _BORV_20_2L
; __CONFIG _CONFIG2H, _WDT_OFF_2H & _WDTPS_32K_2H
; __CONFIG _CONFIG3H, _MCLRE_ON_3H
; __CONFIG _CONFIG4L, _DEBUG_OFF_4L & _LVP_ON_4L & _STVR_ON_4L
; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L
; __CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H
; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L
; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H
; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L
; __CONFIG _CONFIG7H, _EBTRB_OFF_7H
;Configuration Byte 1H Options
_IESO_ON_1H EQU H'FF' ; Internal External Oscillator Switch Over mode enabled
_IESO_OFF_1H EQU H'7F' ; Internal External Oscillator Switch Over mode disabled
_FSCM_ON_1H EQU H'FF' ; Fail Safe Clock Monitor enabled
_FSCM_OFF_1H EQU H'BF' ; Fail Safe Clock Monitor disabled
_RC_OSC_1H EQU H'FF' ; External RC on OSC1, OSC2 as Fosc/4
_RCIO_OSC_1H EQU H'F7' ; External RC on OSC1, OSC2 as RA6
_LP_OSC_1H EQU H'F0' ; LP Oscillator
_XT_OSC_1H EQU H'F1' ; XT Oscillator
_HS_OSC_1H EQU H'F2' ; HS Oscillator
_HSPLL_OSC_1H EQU H'F6' ; HS + PLL
_EC_OSC_1H EQU H'F4' ; External Clock on OSC1, OSC2 as Fosc/4
_ECIO_OSC_1H EQU H'F5' ; External Clock on OSC1, OSC2 as RA6
_INTIO1_OSC_1H EQU H'F9' ; Internal RC, OSC1 as RA7, OSC2 as Fosc/4
_INTIO2_OSC_1H EQU H'F8' ; Internal RC, OSC1 as RA7, OSC2 as RA6
;Configuration Byte 2L Options
_BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v
_BORV_27_2L EQU H'FB' ; 2.7v
_BORV_42_2L EQU H'F7' ; 4.2v
_BORV_45_2L EQU H'F3' ; 4.5v
_BOR_ON_2L EQU H'FF' ; Brown-Out Reset enabled
_BOR_OFF_2L EQU H'FD' ; Brown-Out Reset disabled
_PWRT_OFF_2L EQU H'FF' ; Power-Up Timer disabled
_PWRT_ON_2L EQU H'FE' ; Power-Up Timer enabled
;Configuration Byte 2H Options
_WDT_ON_2H EQU H'FF' ; Watch Dog Timer enabled
_WDT_OFF_2H EQU H'FE' ; Watch Dog Timer disabled
_WDTPS_32K_2H EQU H'FF' ; 1:32,768 WDT Postscaler ratio
_WDTPS_16K_2H EQU H'FD' ; 1:16,384
_WDTPS_8K_2H EQU H'FB' ; 1: 8,192
_WDTPS_4K_2H EQU H'F9' ; 1: 4,096
_WDTPS_2K_2H EQU H'F7' ; 1: 2,048
_WDTPS_1K_2H EQU H'F5' ; 1: 1,024
_WDTPS_512_2H EQU H'F3' ; 1: 512
_WDTPS_256_2H EQU H'F1' ; 1: 256
_WDTPS_128_2H EQU H'EF' ; 1: 128
_WDTPS_64_2H EQU H'ED' ; 1: 64
_WDTPS_32_2H EQU H'EB' ; 1: 32
_WDTPS_16_2H EQU H'E9' ; 1: 16
_WDTPS_8_2H EQU H'E7' ; 1: 8
_WDTPS_4_2H EQU H'E5' ; 1: 4
_WDTPS_2_2H EQU H'E3' ; 1: 2
_WDTPS_1_2H EQU H'E1' ; 1: 1
;Configuration Byte 3H Options
_MCLRE_ON_3H EQU H'FF' ; MCLR enabled, RA5 input disabled
_MCLRE_OFF_3H EQU H'7F' ; MCLR disabled, RA5 input enabled
;Configuration Byte 4L Options
_DEBUG_ON_4L EQU H'7F' ; BacKground deBUGger enabled
_DEBUG_OFF_4L EQU H'FF' ; BacKground deBUGger disabled
_LVP_ON_4L EQU H'FF' ; Low Voltage Prgramming enabled
_LVP_OFF_4L EQU H'FB' ; Low Voltage Prgramming disabled
_STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enabled
_STVR_OFF_4L EQU H'FE' ; Stack over/underflow Reset disabled
;Configuration Byte 5L Options
; Protect program memory blocks from programmer reads and writes (see Config Byte 6L)
_CP0_ON_5L EQU H'FE' ; Block 0 protected
_CP0_OFF_5L EQU H'FF' ; Block 0 readable/ may be writable
_CP1_ON_5L EQU H'FD' ; Block 1 protected
_CP1_OFF_5L EQU H'FF' ; Block 1 readable/ may be writable
;Configuration Byte 5H Options
; Protect blocks from programmer reads and writes (see Config Byte 6H)
_CPB_ON_5H EQU H'BF' ; Boot Block protected
_CPB_OFF_5H EQU H'FF' ; Boot Block readable / may be writable
_CPD_ON_5H EQU H'7F' ; Data EE memory protected
_CPD_OFF_5H EQU H'FF' ; Data EE memory readable / may be writable
;Configuration Byte 6L Options
; Protect program memory blocks from table writes and programmer writes
_WRT0_ON_6L EQU H'FE' ; Block 0 write protected
_WRT0_OFF_6L EQU H'FF' ; Block 0 writable
_WRT1_ON_6L EQU H'FD' ; Block 1 write protected
_WRT1_OFF_6L EQU H'FF' ; Block 1 writable
;Configuration Byte 6H Options
; Protect blocks from table writes and programmer writes
_WRTC_ON_6H EQU H'DF' ; Config registers write protected
_WRTC_OFF_6H EQU H'FF' ; Config registers writable
_WRTB_ON_6H EQU H'BF' ; Boot block write protected
_WRTB_OFF_6H EQU H'FF' ; Boot block writable
_WRTD_ON_6H EQU H'7F' ; Data EE write protected
_WRTD_OFF_6H EQU H'FF' ; Data EE writable
;Configuration Byte 7L Options
; Protect program memory blocks from table reads executed from other blocks
_EBTR0_ON_7L EQU H'FE' ; Block 0 protected
_EBTR0_OFF_7L EQU H'FF' ; Block 0 readable
_EBTR1_ON_7L EQU H'FD' ; Block 1 protected
_EBTR1_OFF_7L EQU H'FF' ; Block 1 readable
;Configuration Byte 7H Options
; Protect block from table reads executed in other blocks
_EBTRB_ON_7H EQU H'BF' ; Boot block read protected
_EBTRB_OFF_7H EQU H'FF' ; Boot block readable
;=======================================================================
;
; Device ID registers
;
; The following is an assignment of address values for the Device ID
; registers for the purpose of table reads.
_DEVID1 EQU H'3FFFFE'
_DEVID2 EQU H'3FFFFF'
; Device ID registers hold device ID and revision number and are
; read-only
;
;Device ID Register 1
; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0
;
;Device ID Register 2
; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3
;=======================================================================
LIST
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