📄 4046.mdf
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LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design: 4046
Doc. no.: 4046/1
Revision: 1.0
Author: EA
Created: 22/06/03
Modified: 29/02/04
*PROPERTIES,1
TGQ=?
*MAPPINGS,3,VALUE+VOLTAGE
4046+5V : TDLHCQ=700n, TDHLCQ=450n, TDLHCQB=700n, TDHLCQB=450n, TDHLOUT=200n,TDLHOUT=200n,TPHZ=450n,TGQ=?
4046+10V : TDLHCQ=300n, TDHLCQ=200n, TDLHCQB=300n, TDHLCQB=200n, TDHLOUT=100n,TDLHOUT=100n,TPHZ=200n,TGQ=?
4046+15V : TDLHCQ=200n, TDHLCQ=190n, TDLHCQB=200n, TDHLCQB=190n,TDHLOUT=80n,TDLHOUT=80n,TPHZ=190n,TGQ=?
*MODELDEFS,6
LX_D_LED : ISAT=1E-14, N=3, RS=2, BV=15.0, CJO=50pF
LX_D_POW : ISAT=10u,RS=1,CJO=20p,TT=50n
LX_D_SCHB : ISAT=100n,RS=12,CJO=1p,TT=5n,EG=0.69
LX_D_SS : ISAT=10n,RS=10,CJO=2p,TT=10n
LX_D_SSG : ISAT=1u,RS=15,CJO=1p,TT=8n,EG=0.67
LX_D_ZEN : ISAT=10n,RS=5,CJO=1p,TT=1n
*PARTLIST,12
ACS1,ACS,"0.00003*V(A,B)",PRIMITIVE=ANALOGUE
AVS1,AVS,"1.0*V(A,B)",PRIMITIVE=ANALOGUE
D1,DIODE,3EZ4V7D5,BV=4.7,IBV=160.0m,MODEL=LX_D_ZEN,MODFILE=DIODE,PRIMITIVE=ANALOG
R1,RESISTOR,10k,PRIMITIVE=ANALOGUE
SW1,DSWITCH,DSWITCH,INVERT=EN,PRIMITIVE=PASSIVE,ROFF=0.1,RON=1000M,TSWITCH=<TPHZ>
SW2,DSWITCH,DSWITCH,PRIMITIVE=PASSIVE,ROFF=1000M,RON=0.1,TSWITCH=<TPHZ>
SW3,DSWITCH,DSWITCH,PRIMITIVE=PASSIVE,ROFF=1000M,RON=1,TSWITCH=1u
U1,DTFF,DTFF,PRIMITIVE=DIGITAL,TDRQ=<TDLHCQ>,TDRQB=<TDLHCQB>
U2,DTFF,DTFF,PRIMITIVE=DIGITAL,TDRQ=<TDLHCQ>,TDRQB=<TDLHCQB>
U3,XOR_2,XOR_2,PRIMITIVE=DIGITAL,TDHLDQ=<TDHLOUT>,TDLHDQ=<TDLHOUT>
U4,VCO,VCO,INIT=0,MAXF=<FREQRANGE>,MAXVIN=<VOLTAGE>,MINF=<FREQOFFSET>,MINVIN=0,MODDLL=VCO.DLL,PRIMITIVE=DIGITAL,THL=<TDHLOUT>,TLH=<TDLHOUT>
U5,INVERTER,INVERTER,PRIMITIVE=DIGITAL
*NETLIST,18
#00000,1
U1,OP,Q
#00001,2
U1,OP,!Q
SW1,IP,EN
#00002,2
U2,OP,Q
SW2,IP,EN
#00003,3
U4,IP,EN
U5,OP,Q
SW3,IP,EN
#00004,2
SW3,IO,A
AVS1,PS,+
#00005,3
SW3,IO,B
ACS1,PS,A
R1,PS,2
SIGIN,4
SIGIN,IT
U2,IP,RESET
U1,IP,CLK
U3,IP,D1
COMPIN,4
COMPIN,IT
U2,IP,CLK
U1,IP,RESET
U3,IP,D0
PC2OUT,3
PC2OUT,OT
SW1,IO,A
SW2,IO,A
PP,2
PP,OT
U2,OP,!Q
PC1OUT,2
PC1OUT,OT
U3,OP,Q
VCOIN,3
VCOIN,IT
U4,IP,VIN
AVS1,PS,A
VCOOUT,2
VCOOUT,OT
U4,PS,DOUT
INH,2
INH,IT
U5,IP,D
GND,13
CX1,GT
CX2,GT
R1,GT
GND,PR
R2,GT
AVS1,PS,B
AVS1,PS,-
ACS1,PS,B
R1,PS,1
D1,PS,A
SW2,IO,B
U1,IP,SET
U2,IP,SET
ZENER,2
ZENER,IT
D1,PS,K
VCC,5
VCC,PR
ACS1,PS,+
SW1,IO,B
U1,IP,D
U2,IP,D
DEMOD,2
DEMOD,OT
ACS1,PS,-
*GATES,0
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