mc14569.mdf

该应用软件可以实现大多数单片机的仿真实验

LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Documents and Settings\bubba\Desktop\MC14569.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  25/10/03
Modified: 27/10/03

*PROPERTIES,0    

*MODELDEFS,0    

*PARTLIST,16   
U1,COUNTER_4,COUNTER_4,ALOAD=0,ARESET=0,LOWER=0,PRIMITIVE=DIGITAL,RESET=10,UPPER=15,USEDIR=0
U2,COUNTER_4,COUNTER_4,ALOAD=0,ARESET=0,LOWER=0,PRIMITIVE=DIGITAL,RESET=10,UPPER=15,USEDIR=0
U3,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U4,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U7,AND_4,AND_4,INVERT="D0,D1,D2",PRIMITIVE=DIGITAL
U8,AND_4,AND_4,INVERT=D0,PRIMITIVE=DIGITAL
U9,OR_3,OR_3,PRIMITIVE=DIGITAL
U10,AND_4,AND_4,INVERT="D1,D2",PRIMITIVE=DIGITAL
U11,AND_4,AND_4,INVERT="D1,D2",PRIMITIVE=DIGITAL
U12,AND_4,AND_4,INVERT=D0,PRIMITIVE=DIGITAL
U13,AND_4,AND_4,INVERT="D0,D1,D2",PRIMITIVE=DIGITAL
U14,AORB_1,AORB_1,PRIMITIVE=DIGITAL
U15,AORB_1,AORB_1,PRIMITIVE=DIGITAL
U16,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U17,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U19,INVERTER,INVERTER,PRIMITIVE=DIGITAL

*NETLIST,45   
#00000,4
U1,OP,Q0
U11,IP,D0
U7,IP,D0
U8,IP,D0

#00001,4
U1,OP,Q1
U11,IP,D1
U7,IP,D1
U8,IP,D1

#00002,4
U1,OP,Q2
U11,IP,D2
U7,IP,D2
U8,IP,D2

#00003,4
U1,OP,Q3
U11,IP,D3
U7,IP,D3
U8,IP,D3

#00004,1
U1,IP,UCLK

#00005,2
U1,IP,LOAD
U16,TS,Q

#00006,2
U1,IP,RESET
U3,TS,Q

#00007,3
U1,OP,MIN
U2,IP,DCLK
U9,IP,D2

#00008,1
U1,OP,MAX

#00009,1
U1,IP,CNTUP

#00010,1
U1,OP,RCO

#00011,3
U2,OP,Q0
U10,IP,D0
U13,IP,D0

#00012,5
U2,OP,Q1
U10,IP,D1
U12,IP,D1
U13,IP,D1
U12,IP,D0

#00013,4
U2,OP,Q2
U10,IP,D2
U13,IP,D2
U12,IP,D2

#00014,1
U2,IP,UCLK

#00015,2
U2,IP,LOAD
U17,TS,Q

#00016,2
U2,IP,RESET
U4,TS,Q

#00017,2
U2,OP,MIN
U9,IP,D0

#00018,1
U2,OP,MAX

#00019,1
U2,IP,CNTUP

#00020,1
U2,OP,RCO

#00021,2
U3,IP,D
U11,OP,Q

#00022,2
U4,IP,D
U10,OP,Q

#00023,2
U9,IP,D1
U19,OP,Q

#00024,2
U7,OP,Q
U14,PS,A0

#00025,2
U13,OP,Q
U15,PS,A0

#00026,2
U16,IP,D
U14,PS,Q0

#00027,2
U15,PS,B0
U12,OP,Q

#00028,2
U15,PS,Q0
U17,IP,D

#00029,2
U14,PS,B0
U8,OP,Q

P0,2
P0,IT
U1,IP,D0

P1,2
P1,IT
U1,IP,D1

P2,2
P2,IT
U1,IP,D2

P3,2
P3,IT
U1,IP,D3

CLK,2
CLK,IT
U1,IP,DCLK

VDD,5
VDD,PR
U1,IP,OE
U2,IP,OE
U1,IP,CE
U2,IP,CE

P4,2
P4,IT
U2,IP,D0

P5,2
P5,IT
U2,IP,D1

P6,2
P6,IT
U2,IP,D2

P7,2
P7,IT
U2,IP,D3

Q,5
Q,OT
U2,OP,Q3
U10,IP,D3
U13,IP,D3
U12,IP,D3

CTL1,3
CTL1,IT
U3,IP,OE
U14,PS,ASEL

CTL2,3
CTL2,IT
U4,IP,OE
U15,PS,ASEL

Z/DET,2
Z/DET,OT
U9,OP,Q

CAS/FE,4
CAS/FE,IT
U19,IP,D
U16,IP,OE
U17,IP,OE

*GATES,0