my_radix2_xfft1024.xco

xilinx FFT using ip core project navigator

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\training\SAP\DSP\Projects\UpdatingExample\FFT\81\81i_radix2_xfft1024_v3_1_ver
SET speedgrade = -4
SET simulationfiles = Structural
SET asysymbol = True
SET addpads = False
SET device = xc2v1000
SET implementationfiletype = ngc
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = bg575
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Fast_Fourier_Transform family Xilinx,_Inc. 3.2
# END Select
# BEGIN Parameters
CSET scaling_options=Scaled
CSET create_rpm=false
CSET ce=false
CSET run_time_configurable_transform_length=true
CSET output_data_width=16
CSET output_ordering=Bit_Reversed_Order
CSET fast_phase_factor=false
CSET memory_options_data=Block_Ram
CSET number_of_stages_using_block_ram_for_data_and_phase_factors=3
CSET ovflo=true
CSET rounding_modes=Truncation
CSET component_name=my_radix2_xfft1024
CSET memory_options_phase_factors=Block_Ram
CSET fast_butterfly=false
CSET transform_length=1024
CSET implementation_options=Radix_2_Minimum_Resources
CSET fast_complex_mult=false
CSET sclr=true
CSET optimize_for_speed_using_xtreme_dsp_slices=false
CSET input_width=16
CSET phase_factor_width=16
# END Parameters
GENERATE