📄 my_radix2_xfft1024_readme.txt
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The following files were generated for 'my_radix2_xfft1024' in directory
D:\training\SAP\DSP\Projects\UpdatingExample\FFT\81\81i_radix2_xfft1024_v3_1_ver:
wrap_TRIG_ROM.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
my_radix2_xfft1024.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
my_radix2_xfft1024.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
my_radix2_xfft1024.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
my_radix2_xfft1024.sym:
Please see the core data sheet.
my_radix2_xfft1024.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
my_radix2_xfft1024.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
my_radix2_xfft1024.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
my_radix2_xfft1024.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
my_radix2_xfft1024_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
my_radix2_xfft1024_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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