des.vhd

一个快速实现3des的算法

--#########################################################################
--                                                                       --
--                                                                       --
--  Module      : DES.vhd                                                --
--  Last Update : 08/01/2001                                             --
--                                                                       --
--  Description : DES Top level module                                   --
--                                                                       --
--                                                                       --
--  Designer    : Vikram Pasham                                          --
--  Company     : Xilinx & Inc.                                          --
--                                                                       --
--                                                                       --
--  Disclaimer  : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY    --
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY       --
--                IMPLIED WARRANTIES OF MERCHANTABILITY & FITNESS FOR    --
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.         --
--                THEY ARE ONLY INTENDED TO BE USED BY XILINX            --
--                CUSTOMERS, AND WITHIN XILINX DEVICES.                  --
--                                                                       --
--                Copyright (c) 2000 Xilinx, Inc.                        --
--                All rights reserved                                    --
--                                                                       --
--                                                                       --
--                                                                       --
--#########################################################################


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.des_const.all;

entity DES is
  
  port (
    reset      : in std_logic;
    clk        : in  std_logic;
    data_bus   : in  std_logic_vector(1 to 64);  -- input bus for carrying
                                                 -- en/decrypted data
    e_data_rdy : in std_logic;     -- Signal indicates data bus has valid data 
    key        : in  std_logic_vector(1 to 64);  -- Encryption/Decryption key
    decrypt    : in  std_logic;                  -- 0 = encrypt; 1 = decrypt
    data_out   : out std_logic_vector(1 to 64);  -- en/decrypted data output
    d_data_rdy : out  std_logic);       -- 1 = en/decrypted data is on data_out

end DES;



architecture DES_RTL of DES is

component DES_KEY
generic (cs : std_logic_vector(1 to 5));
  port(clk      : in std_logic;         
       key_in_l : in std_logic_vector(1 to 28);       
       key_in_r : in std_logic_vector(1 to 28);                                
       key_out_l_reg : out std_logic_vector(1 to 28);  
       key_out_r_reg : out std_logic_vector(1 to 28); 
       compressed_key: out std_logic_vector(1 to 48);
       decrypt	: in std_logic);
end component;

component DES_F
port(reset : in std_logic; 
     clk   : in  std_logic;
     f_in_l: in  std_logic_vector(1 to 32);		
     f_in_r: in  std_logic_vector(1 to 32);
     f_out_l_reg: out std_logic_vector(1 to 32);
     f_out_r_reg: out std_logic_vector(1 to 32);
     compressed_key : in  std_logic_vector(1 to 48));
end component;



signal data_bus_reg : std_logic_vector(1 to 64);
signal key_reg      : std_logic_vector(1 to 64);


-- Intermediate states in the en(de)cryption

signal perm_key_l, perm_key_r : std_logic_vector(1 to 28);  -- Permuted key
signal iperm_data_l,  iperm_data_r : std_logic_vector(1 to 32);  
                                                        -- IP encrypted data
signal f_out_rl : std_logic_vector(1 to 64);  -- Final F output
signal reverse_perm : std_logic_vector(1 to 64);   
                                       -- Output of reverse permutation setp
                                    


-- Signals between pipeline blocks - KEYS

signal key1_l, key1_r : std_logic_vector(1 to 28);
signal key2_l, key2_r : std_logic_vector(1 to 28);
signal key3_l, key3_r : std_logic_vector(1 to 28);
signal key4_l, key4_r : std_logic_vector(1 to 28);
signal key5_l, key5_r : std_logic_vector(1 to 28);
signal key6_l, key6_r : std_logic_vector(1 to 28);
signal key7_l, key7_r : std_logic_vector(1 to 28);
signal key8_l, key8_r : std_logic_vector(1 to 28);
signal key9_l, key9_r : std_logic_vector(1 to 28);
signal key10_l, key10_r : std_logic_vector(1 to 28);
signal key11_l, key11_r : std_logic_vector(1 to 28);
signal key12_l, key12_r : std_logic_vector(1 to 28);
signal key13_l, key13_r : std_logic_vector(1 to 28);
signal key14_l, key14_r : std_logic_vector(1 to 28);
signal key15_l, key15_r : std_logic_vector(1 to 28);
signal key16_l, key16_r : std_logic_vector(1 to 28);

signal key1, key2, key3, key4 : std_logic_vector(1 to 48);
signal key5, key6, key7, key8 : std_logic_vector(1 to 48);
signal key9, key10, key11, key12: std_logic_vector(1 to 48) ;
signal key13, key14, key15, key16 : std_logic_vector(1 to 48);

-- Signals between pipeline blocks - DATA
signal f1_l, f2_l, f3_l, f4_l : std_logic_vector(1 to 32);
signal f5_l, f6_l, f7_l, f8_l : std_logic_vector(1 to 32);
signal f9_l, f10_l, f11_l, f12_l  : std_logic_vector(1 to 32);
signal f13_l, f14_l, f15_l, f16_l : std_logic_vector(1 to 32);

signal f1_r, f2_r, f3_r, f4_r : std_logic_vector(1 to 32) ;
signal f5_r, f6_r, f7_r, f8_r : std_logic_vector(1 to 32) ;
signal f9_r, f10_r, f11_r, f12_r  : std_logic_vector (1 to 32);
signal f13_r, f14_r, f15_r, f16_r : std_logic_vector(1 to 32) ;




-- encrypt/decrypt and data_valid flags


signal decrypt1, decrypt2, decrypt3, decrypt4 :std_logic ;
signal decrypt5, decrypt6, decrypt7, decrypt8 :std_logic;
signal decrypt9, decrypt10, decrypt11, decrypt12 :std_logic;
signal decrypt13, decrypt14, decrypt15 :std_logic;
signal e_data_rdy_reg, decrypt_reg : std_logic;

signal decrypt1_reg, decrypt2_reg :std_logic_vector(1 to 3);
signal decrypt3_reg, decrypt4_reg :std_logic_vector(1 to 3);
signal decrypt5_reg, decrypt6_reg :std_logic_vector(1 to 3); 
signal decrypt7_reg, decrypt8_reg :std_logic_vector(1 to 3);
signal decrypt9_reg, decrypt10_reg  :std_logic_vector(1 to 3); 
signal decrypt11_reg, decrypt12_reg :std_logic_vector(1 to 3); 
signal decrypt13_reg, decrypt14_reg :std_logic_vector(1 to 3);
signal decrypt15_reg :std_logic_vector(1 to 3);

signal count : integer range 0 to 50;

begin  -- DES_RTL

process(reset, clk, e_data_rdy)
begin
   if(reset = '1') then
     data_bus_reg  <= (others => '0');
     key_reg <= (others => '0');
     e_data_rdy_reg <= '0';
     decrypt_reg <= '0';
   elsif(clk'event and clk = '1') then
     data_bus_reg <= data_bus;
     key_reg <= key;
     e_data_rdy_reg <= e_data_rdy;
     decrypt_reg <=  decrypt;

   end if;
end process;

--////////////////////////////////////////////// --
-- Counter to count upto 48 and assert d_data_rdy
-- indicating valid data on the output.
--//////////////////////////////////////////////--


process(reset, clk)
begin
  if(reset = '1') then
      count <= 0;
  elsif( clk'event and clk = '1') then
    if(count < 48 and e_data_rdy_reg = '1') then
      count <= count + 1;
    end if;
  end if;


end process;
d_data_rdy <= '1' when (count = 48) else
	      '0';

process(clk)
begin
  if(clk'event and clk = '1') then
    decrypt1_reg  <= decrypt_reg & decrypt1_reg(1 to 2);
    decrypt2_reg  <= decrypt1_reg(3) & decrypt2_reg(1 to 2);
    decrypt3_reg  <= decrypt2_reg(3) & decrypt3_reg(1 to 2);
    decrypt4_reg  <= decrypt3_reg(3) & decrypt4_reg(1 to 2);
    decrypt5_reg  <= decrypt4_reg(3) & decrypt5_reg(1 to 2);
    decrypt6_reg  <= decrypt5_reg(3) & decrypt6_reg(1 to 2);
    decrypt7_reg  <= decrypt6_reg(3) & decrypt7_reg(1 to 2);
    decrypt8_reg  <= decrypt7_reg(3) & decrypt8_reg(1 to 2);
    decrypt9_reg  <= decrypt8_reg(3) & decrypt9_reg(1 to 2);
    decrypt10_reg  <= decrypt9_reg(3) & decrypt10_reg(1 to 2);
    decrypt11_reg  <= decrypt10_reg(3) & decrypt11_reg(1 to 2);