tm-m88k.h

arm-linux-gcc编译器

/* Target machine description for generic Motorola 88000, for GDB.
   Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

/* g++ support is not yet included.  */

/* Define the bit, byte, and word ordering of the machine.  */
#define TARGET_BYTE_ORDER BIG_ENDIAN

/* We cache information about saved registers in the frame structure,
   to save us from having to re-scan function prologues every time
   a register in a non-current frame is accessed.  */

#define EXTRA_FRAME_INFO 	\
	struct frame_saved_regs *fsr;	\
	CORE_ADDR locals_pointer;	\
	CORE_ADDR args_pointer;

/* Zero the frame_saved_regs pointer when the frame is initialized,
   so that FRAME_FIND_SAVED_REGS () will know to allocate and
   initialize a frame_saved_regs struct the first time it is called.
   Set the arg_pointer to -1, which is not valid; 0 and other values
   indicate real, cached values.  */

#define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \
	init_extra_frame_info (fromleaf, fi)
extern void init_extra_frame_info ();

#define IEEE_FLOAT

/* Offset from address of function to start of its code.
   Zero on most machines.  */

#define FUNCTION_START_OFFSET 0

/* Advance PC across any function entry prologue instructions
   to reach some "real" code.  */

extern CORE_ADDR m88k_skip_prologue PARAMS ((CORE_ADDR));
#define SKIP_PROLOGUE(frompc) (m88k_skip_prologue (frompc))

/* The m88k kernel aligns all instructions on 4-byte boundaries.  The
   kernel also uses the least significant two bits for its own hocus
   pocus.  When gdb receives an address from the kernel, it needs to
   preserve those right-most two bits, but gdb also needs to be careful
   to realize that those two bits are not really a part of the address
   of an instruction.  Shrug.  */

extern CORE_ADDR m88k_addr_bits_remove PARAMS ((CORE_ADDR));
#define ADDR_BITS_REMOVE(addr) m88k_addr_bits_remove (addr)

/* Immediately after a function call, return the saved pc.
   Can't always go through the frames for this because on some machines
   the new frame is not set up until the new function executes
   some instructions.  */

#define SAVED_PC_AFTER_CALL(frame) \
  (ADDR_BITS_REMOVE (read_register (SRP_REGNUM)))

/* Stack grows downward.  */

#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))

/* Sequence of bytes for breakpoint instruction.  */

/* instruction 0xF000D1FF is 'tb0 0,r0,511'
   If Bit bit 0 of r0 is clear (always true),
   initiate exception processing (trap).
 */
#define BREAKPOINT {0xF0, 0x00, 0xD1, 0xFF}

/* Amount PC must be decremented by after a breakpoint.
   This is often the number of bytes in BREAKPOINT
   but not always.  */

#define DECR_PC_AFTER_BREAK 0

/* Say how long (ordinary) registers are.  This is a piece of bogosity
   used in push_word and a few other places; REGISTER_RAW_SIZE is the
   real way to know how big a register is.  */

#define REGISTER_SIZE 4

/* Number of machine registers */

#define GP_REGS (38)
#define FP_REGS (32)
#define NUM_REGS (GP_REGS + FP_REGS)

/* Initializer for an array of names of registers.
   There should be NUM_REGS strings in this initializer.  */

#define REGISTER_NAMES {\
			  "r0",\
			  "r1",\
			  "r2",\
			  "r3",\
			  "r4",\
			  "r5",\
			  "r6",\
			  "r7",\
			  "r8",\
			  "r9",\
			  "r10",\
			  "r11",\
			  "r12",\
			  "r13",\
			  "r14",\
			  "r15",\
			  "r16",\
			  "r17",\
			  "r18",\
			  "r19",\
			  "r20",\
			  "r21",\
			  "r22",\
			  "r23",\
			  "r24",\
			  "r25",\
			  "r26",\
			  "r27",\
			  "r28",\
			  "r29",\
			  "r30",\
			  "r31",\
			  "psr",\
			  "fpsr",\
			  "fpcr",\
			  "sxip",\
			  "snip",\
			  "sfip",\
			  "x0",\
			  "x1",\
			  "x2",\
			  "x3",\
			  "x4",\
			  "x5",\
			  "x6",\
			  "x7",\
			  "x8",\
			  "x9",\
			  "x10",\
			  "x11",\
			  "x12",\
			  "x13",\
			  "x14",\
			  "x15",\
			  "x16",\
			  "x17",\
			  "x18",\
			  "x19",\
			  "x20",\
			  "x21",\
			  "x22",\
			  "x23",\
			  "x24",\
			  "x25",\
			  "x26",\
			  "x27",\
			  "x28",\
			  "x29",\
			  "x30",\
			  "x31",\
			  "vbr",\
			  "dmt0",\
			  "dmd0",\
			  "dma0",\
			  "dmt1",\
			  "dmd1",\
			  "dma1",\
			  "dmt2",\
			  "dmd2",\
			  "dma2",\
			  "sr0",\
			  "sr1",\
			  "sr2",\
			  "sr3",\
			  "fpecr",\
			  "fphs1",\
			  "fpls1",\
			  "fphs2",\
			  "fpls2",\
			  "fppt",\
			  "fprh",\
			  "fprl",\
			  "fpit",\
			  "fpsr",\
			  "fpcr",\
		      }


/* Register numbers of various important registers.
   Note that some of these values are "real" register numbers,
   and correspond to the general registers of the machine,
   and some are "phony" register numbers which are too large
   to be actual register numbers as far as the user is concerned
   but do serve to get the desired values when passed to read_register.  */

#define R0_REGNUM 0		/* Contains the constant zero */
#define SRP_REGNUM 1		/* Contains subroutine return pointer */
#define RV_REGNUM 2		/* Contains simple return values */
#define SRA_REGNUM 12		/* Contains address of struct return values */
#define SP_REGNUM 31		/* Contains address of top of stack */

/* Instruction pointer notes...

   On the m88100:

   * cr04 = sxip.  On exception, contains the excepting pc (probably).
   On rte, is ignored.

   * cr05 = snip.  On exception, contains the NPC (next pc).  On rte,
   pc is loaded from here.

   * cr06 = sfip.  On exception, contains the NNPC (next next pc).  On
   rte, the NPC is loaded from here.

   * lower two bits of each are flag bits.  Bit 1 is V means address
   is valid.  If address is not valid, bit 0 is ignored.  Otherwise,
   bit 0 is E and asks for an exception to be taken if this
   instruction is executed.

   On the m88110:

   * cr04 = exip.  On exception, contains the address of the excepting
   pc (always).  On rte, pc is loaded from here.  Bit 0, aka the D
   bit, is a flag saying that the offending instruction was in a
   branch delay slot.  If set, then cr05 contains the NPC.

   * cr05 = enip.  On exception, if the instruction pointed to by cr04
   was in a delay slot as indicated by the bit 0 of cr04, aka the D
   bit, the cr05 contains the NPC.  Otherwise ignored.

   * cr06 is invalid  */

/* Note that the Harris Unix kernels emulate the m88100's behavior on
   the m88110.  */

#define SXIP_REGNUM 35		/* On m88100, Contains Shadow Execute
				   Instruction Pointer.  */
#define SNIP_REGNUM 36		/* On m88100, Contains Shadow Next
				   Instruction Pointer.  */
#define SFIP_REGNUM 37		/* On m88100, Contains Shadow Fetched
				   Intruction pointer.  */

#define EXIP_REGNUM 35		/* On m88110, Contains Exception
				   Executing Instruction Pointer.  */
#define ENIP_REGNUM 36		/* On m88110, Contains the Exception
				   Next Instruction Pointer.  */

#define PC_REGNUM SXIP_REGNUM	/* Program Counter */
#define NPC_REGNUM SNIP_REGNUM	/* Next Program Counter */
#define NNPC_REGNUM SFIP_REGNUM	/* Next Next Program Counter */

#define PSR_REGNUM 32		/* Processor Status Register */
#define FPSR_REGNUM 33		/* Floating Point Status Register */
#define FPCR_REGNUM 34		/* Floating Point Control Register */
#define XFP_REGNUM 38		/* First Extended Float Register */
#define X0_REGNUM XFP_REGNUM	/* Which also contains the constant zero */

/* This is rather a confusing lie.  Our m88k port using a stack pointer value
   for the frame address.  Hence, the frame address and the frame pointer are
   only indirectly related.  The value of this macro is the register number
   fetched by the machine "independent" portions of gdb when they want to know
   about a frame address.  Thus, we lie here and claim that FP_REGNUM is
   SP_REGNUM.  */
#define FP_REGNUM SP_REGNUM	/* Reg fetched to locate frame when pgm stops */
#define ACTUAL_FP_REGNUM 30

/* PSR status bit definitions.  */

#define PSR_MODE		0x80000000
#define PSR_BYTE_ORDER		0x40000000
#define PSR_SERIAL_MODE		0x20000000
#define PSR_CARRY		0x10000000
#define PSR_SFU_DISABLE		0x000003f0
#define PSR_SFU1_DISABLE	0x00000008
#define PSR_MXM			0x00000004
#define PSR_IND			0x00000002
#define PSR_SFRZ		0x00000001



/* The following two comments come from the days prior to the m88110
   port.  The m88110 handles the instruction pointers differently.  I
   do not know what any m88110 kernels do as the m88110 port I'm
   working with is for an embedded system.  [e-mail]
   13-sept-93.  */

/* BCS requires that the SXIP_REGNUM (or PC_REGNUM) contain the
   address of the next instr to be executed when a breakpoint occurs.
   Because the kernel gets the next instr (SNIP_REGNUM), the instr in
   SNIP needs to be put back into SFIP, and the instr in SXIP should
   be shifted to SNIP */